AT80C51SND1C-ROTIL Atmel, AT80C51SND1C-ROTIL Datasheet - Page 179

• Manufacturer Part Number: AT80C51SND1C-ROTIL
• Description: IC MCU FLASH MP3 DECODER 80-TQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51SND1C-ROTIL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Type: ROMless
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: AT80C51SND1CROTIL

22. Keyboard Interface
22.1
22.1.1
22.2
4109L–8051–02/08
Description
Registers
Power Reduction Mode
The AT8xC51SND1C implement a keyboard interface allowing the connection of a 4 x n matrix
keyboard. It is based on 4 inputs with programmable interrupt capability on both high or low
level. These inputs are available as alternate function of P1.3:0 and allow exit from idle and
power down modes.
The keyboard interfaces with the C51 core through 2 special function registers: KBCON, the
keyboard control register (see Table 152); and KBSTA, the keyboard control and status register
(see Table 153).
The keyboard inputs are considered as 4 independent interrupt sources sharing the same inter-
rupt vector. An interrupt enable bit (EKB in IEN1 register) allows global enable or disable of the
keyboard interrupt (see Figure 22-1). As detailed in Figure 22-2 each keyboard input has the
capability to detect a programmable level according to KINL3:0 bit value in KBCON register.
Level detection is then reported in interrupt flags KINF3:0 in KBSTA register.
A keyboard interrupt is requested each time one of the four flags is set, i.e. the input level
matches the programmed one. Each of these four flags can be masked by software using
KINM3:0 bits in KBCON register and is cleared by reading KBSTA register.
This structure allows keyboard arrangement from 1 by n to 4 by n matrix and allow usage of KIN
inputs for any other purposes.
Figure 22-1. Keyboard Interface Block Diagram
Figure 22-2. Keyboard Input Circuitry
KIN3:0 inputs allow exit from idle and power-down modes as detailed in section “Power Man-
agement”, page 48. To enable this feature, KPDE bit in KBSTA register must be set to logic 1.
Due to the asynchronous keypad detection in power down mode (all clocks are stopped), exit
may happen on parasitic key press. In this case, no key is detected and software must enter
power down again.
Table 152. KBCON Register
KIN3:0
KIN0
KIN1
KIN2
KIN3
Input Circuitry
Input Circuitry
Input Circuitry
Input Circuitry
KBCON.7:4
KINL3:0
0
1
KBSTA.3:0
KINF3:0
AT8xC51SND1C
IEN1.4
EKB
KBCON.3:0
KINM3:0
Keyboard Interface
Interrupt Request
179