AT80C51SND1C-ROTIL Atmel, AT80C51SND1C-ROTIL Datasheet - Page 123

• Manufacturer Part Number: AT80C51SND1C-ROTIL
• Description: IC MCU FLASH MP3 DECODER 80-TQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51SND1C-ROTIL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Type: ROMless
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: AT80C51SND1CROTIL

Figure 16-20. Data Block Reception Flows
16.6.5
16.7
16.7.1
4109L–8051–02/08
Interrupt
Flow Control
Description
read 8 data from MMDAT
a. Polling mode
Start Transmission
F1EI or F2EI = 1?
FIFO Reading
No More Data
Data Block
To Receive?
Reception
DATEN = 1
DATEN = 0
FIFO Full?
To allow transfer at high speed without taking care of CPU oscillator frequency, the FLOWC bit
in MMCON2 allows control of the data flow in both transmission and reception.
During transmission, setting the FLOWC bit has the following effects:
•
•
During reception, setting the FLOWC bit has the following effects:
•
•
As soon as the clock is stopped, the MMC bus is frozen and remains in its state until the clock is
restored by writing or reading data in MMDAT.
As shown in Figure 16-21, the MMC controller implements eight interrupt sources reported in
MCBI, EORI, EOCI, EOFI, F2FI, F1FI, and F2EI flags in MMCINT register. These flags are
detailed in the previous sections.
All these sources are maskable separately using MCBM, EORM, EOCM, EOFM, F2FM, F1FM,
and F2EM mask bits respectively in MMMSK register.
MMCLK is stopped when both FIFOs become empty: F1EI and F2EI set.
MMCLK is restarted when one of the FIFOs becomes full: F1EI or F2EI cleared.
MMCLK is stopped when both FIFOs become full: F1FI and F2FI set.
MMCLK is restarted when one of the FIFOs becomes empty: F1FI or F2FI cleared.
Unmask FIFOs Full
Start Transmission
Initialization
Data Block
DATEN = 1
DATEN = 0
F1FM = 0
F2FM = 0
b. Interrupt mode
read 8 data from MMDAT
F1EI or F2EI = 1?
Reception ISR
Mask FIFOs Full
FIFO Reading
No More Data
AT8xC51SND1C
Data Block
To Receive?
FIFO Full?
F1FM = 1
F2FM = 1
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