ATMEGA162V-8AJ Atmel, ATMEGA162V-8AJ Datasheet - Page 44

• Manufacturer Part Number: ATMEGA162V-8AJ
• Description: IC MCU AVR 16K 5V 8MHZ 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162V-8AJ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -

Extended MCU
Control Register –
EMCUCR
Idle Mode
Power-down Mode
44
ATmega162/V
• Bit 7 – SM0: Sleep Mode Select Bit 0
The Sleep Mode Select bits select between the five available sleep modes as shown in
16.
Table 16. Sleep Mode Select
Note:
When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, Timer/Counters,
Watchdog, and the interrupt system to continue operating. This sleep mode basically halts
clk
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the
Analog Comparator interrupt is not required, the Analog Comparator can be powered down by
setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will
reduce power consumption in Idle mode.
When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-
down mode. In this mode, the external Oscillator is stopped, while the external interrupts and the
Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-
out Reset, an External Level Interrupt on INT0 or INT1, an external interrupt on INT2, or a pin
change interrupt can wake up the MCU. This sleep mode basically halts all generated clocks,
allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. Refer to
for details.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the
Reset Time-out period, as described in
Bit
Read/Write
Initial Value
CPU
SM2
0
0
0
0
1
1
1
1
and clk
1. Standby mode and Extended Standby mode are only available with external crystals or
resonators.
FLASH
SM0
R/W
7
0
, while allowing the other clocks to run.
SM1
0
0
1
1
0
0
1
1
SRL2
R/W
6
0
SRL1
R/W
5
0
SM0
0
1
0
1
0
1
0
1
SRL0
R/W
“Clock Sources” on page
4
0
Sleep Mode
Idle
Reserved
Power-down
Power-save
Reserved
Reserved
Standby
Extended Standby
SRW01
R/W
3
0
(1)
SRW00
R/W
2
0
(1)
SRW11
“External Interrupts” on page 84
R/W
36.
1
0
ISC2
R/W
0
0
EMCUCR
2513K–AVR–07/09
Table