ATMEGA162V-8AJ Atmel, ATMEGA162V-8AJ Datasheet - Page 246

• Manufacturer Part Number: ATMEGA162V-8AJ
• Description: IC MCU AVR 16K 5V 8MHZ 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162V-8AJ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -

SPI Serial
Programming
Algorithm
246
ATmega162/V
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low:> 2 CPU clock cycles for f
High:> 2 CPU clock cycles for f
When writing serial data to the ATmega162, data is clocked on the rising edge of SCK.
When reading data from the ATmega162, data is clocked on the falling edge of SCK. See
106.
To program and verify the ATmega162 in the SPI Serial Programming mode, the following
sequence is recommended (See four byte instruction formats in
1. Power-up sequence:
2. Wait for at least 20 ms and enable SPI Serial Programming by sending the Programming
3. The SPI Serial Programming instructions will not work if the communication is out of syn-
4. The Flash is programmed one page at a time. The page size is found in
5. The EEPROM array can either be programmed one page at a time or it can be pro-
For Page Programming, the following algorithm is used:
Alternatively, the EEPROM can be programmed bytewise:
6. Any memory location can be verified by using the Read instruction which returns the con-
Apply power between V
tems, the programmer can not guarantee that SCK is held low during Power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
Enable serial instruction to pin MOSI.
chronization. When in sync. the second byte (0x53), will echo back when issuing the third
byte of the Programming Enable instruction. Whether the echo is correct or not, all four
bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a
positive pulse and issue a new Programming Enable command.
page
address and data together with the Load Program Memory Page instruction. To ensure
correct loading of the page, the data low byte must be loaded before data high byte is
applied for a given address. The Program Memory Page is stored by loading the Write
Program Memory Page instruction with the 8 MSB of the address. If polling is not used,
the user must wait at least t
Accessing the SPI serial programming interface before the Flash write operation com-
pletes can result in incorrect programming.
grammed byte by byte.
The EEPROM memory page is loaded one byte at a time by supplying the 2 LSB of the
address and data together with the Load EEPROM Memory Page instruction. The EEPROM
Memory Page is stored by loading the Write EEPROM Memory Page instruction with the 8
MSB of the address. If polling is not used, the user must wait at least t
ing the next page. (See
the EEPROM write operation completes can result in incorrect programming.
The EEPROM array is programmed one byte at a time by supplying the address and data
together with the Write EEPROM instruction. An EEPROM memory location is first automat-
ically erased before new data is written. If polling is not used, the user must wait at least
t
in the data file(s) need to be programmed.
tent at the selected address at serial output MISO.
WD_EEPROM
236. The memory page is loaded one byte at a time by supplying the 6 LSB of the
before issuing the next byte. (See
CC
Table
ck
and GND while RESET and SCK are set to “0”. In some sys-
ck
WD_FLASH
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
99.) Accessing the SPI Serial Programming interface before
before issuing the next page. (See
Table
109.) In a chip erased device, no 0xFFs
Table
ck
ck
>= 12 MHz
>= 12 MHz
110):
WD_EEPROM
Table
Table 105 on
2513K–AVR–07/09
109.)
before issu-
Figure