ATMEGA162V-8AJ Atmel, ATMEGA162V-8AJ Datasheet - Page 145

• Manufacturer Part Number: ATMEGA162V-8AJ
• Description: IC MCU AVR 16K 5V 8MHZ 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162V-8AJ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -

Fast PWM Mode
2513K–AVR–07/09
The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 1) provides a high frequency
PWM waveform generation option. The fast PWM differs from the other PWM option by its sin-
gle-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In
non-inverting Compare Output mode, the Output Compare (OC2) is cleared on the Compare
Match between TCNT2 and OCR2, and set at BOTTOM. In inverting Compare Output mode, the
output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the
operating frequency of the fast PWM mode can be twice as high as the phase correct PWM
mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited
for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the MAX value.
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
PWM mode is shown in
gram for illustrating the single-slope operation. The diagram includes non-inverted and inverted
PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare
matches between OCR2 and TCNT2.
Figure 64. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (
rupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Set-
ting the COM21:0 bits to two will produce a non-inverted PWM and an inverted PWM output can
be generated by setting the COM21:0 to three (See
value will only be visible on the port pin if the data direction for the port pin is set as output. The
PWM waveform is generated by setting (or clearing) the OC2 Register at the Compare Match
between OCR2 and TCNT2, and clearing (or setting) the OC2 Register at the timer clock cycle
the counter is cleared (changes from MAX to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
TCNTn
OCn
OCn
Period
1
Figure
2
64. The TCNT2 value is in the timing diagram shown as a histo-
TOV2
3
f
OCnPWM
) is set each time the counter reaches MAX. If the inter-
4
=
----------------- -
N 256
f
clk_I/O
⋅
5
Table 62 on page
6
OCRn Interrupt Flag Set
OCRn Update and
TOVn Interrupt Flag Set
ATmega162/V
7
(COMn1:0 = 2)
(COMn1:0 = 3)
150). The actual OC2
145