ATMEGA162V-8AJ Atmel, ATMEGA162V-8AJ Datasheet - Page 180

• Manufacturer Part Number: ATMEGA162V-8AJ
• Description: IC MCU AVR 16K 5V 8MHZ 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162V-8AJ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -

Asynchronous Data
Recovery
180
ATmega162/V
Figure 79. Start Bit Sampling
When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the
start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in
the figure. The clock recovery logic then uses samples 8, 9 and 10 for Normal mode, and sam-
ples 4, 5 and 6 for Double Speed mode (indicated with sample numbers inside boxes on the
figure), to decide if a valid start bit is received. If two or more of these three samples have logical
high levels (the majority wins), the start bit is rejected as a noise spike and the receiver starts
looking for the next high to low-transition. If however, a valid start bit is detected, the clock recov-
ery logic is synchronized and the data recovery can begin. The synchronization process is
repeated for each start bit.
When the receiver clock is synchronized to the start bit, the data recovery can begin. The data
recovery unit uses a state machine that has 16 states for each bit in Normal mode and 8 states
for each bit in Double Speed mode.
bit. Each of the samples is given a number that is equal to the state of the recovery unit.
Figure 80. Sampling of Data and Parity Bit
The decision of the logic level of the received bit is taken by doing a majority voting of the logic
value to the three samples in the center of the received bit. The center samples are emphasized
on the figure by having the sample number inside boxes. The majority voting process is done as
follows: If two or all three samples have high levels, the received bit is registered to be a logic 1.
If two or all three samples have low levels, the received bit is registered to be a logic 0. This
majority voting process acts as a low pass filter for the incoming signal on the RxD pin. The
recovery process is then repeated until a complete frame is received. Including the first stop bit.
Note that the receiver only uses the first stop bit of a frame.
Figure 81
the next frame.
(U2X = 0)
(U2X = 1)
(U2X = 0)
(U2X = 1)
Sample
Sample
Sample
Sample
RxD
RxD
shows the sampling of the stop bit and the earliest possible beginning of the start bit of
0
0
IDLE
0
1
1
1
1
2
2
3
2
3
2
4
4
Figure 80
5
3
5
3
6
6
7
4
7
4
shows the sampling of the data bits and the parity
8
8
START
BIT n
9
5
9
5
10
10
11
11
6
6
12
12
13
13
7
7
14
14
15
15
8
8
16
16
1
1
1
1
2513K–AVR–07/09
2
BIT 0
3
2