ATMEGA64-16AI Atmel, ATMEGA64-16AI Datasheet - Page 82

• Manufacturer Part Number: ATMEGA64-16AI
• Description: IC AVR MCU 64K 16MHZ IND 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2490Q–AVR–06/10
• AIN0/XCK0 – Port E, Bit 2
AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of
the Analog Comparator.
XCK0, USART0 External Clock. The Data Direction Register (DDE2) controls whether the clock
is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active only when the USART0
operates in synchronous mode.
• PDO/TXD0 – Port E, Bit 1
PDO, SPI Serial Programming Data output. During Serial Program Downloading, this pin is used
as data output line for the ATmega64.
TXD0, UART0 Transmit Pin.
• PDI/RXD0 – Port E, Bit 0
PDI, SPI Serial Programming Data input. During serial program downloading, this pin is used as
data input line for the ATmega64.
RXD0, USART0 Receive pin. Receive Data (Data Input pin for the USART0). When the
USART0 Receiver is enabled this pin is configured as an input regardless of the value of
DDRE0. When the USART0 forces this pin to be an input, a logical one in PORTE0 will turn on
the internal pull-up.
Table 40
Figure 33 on page
Table 40. Overriding Signals for Alternate Functions PE7..PE4
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
and
PE7/INT7/ICP3
0
0
0
0
0
0
INT7 ENABLE
1
INT7 INPUT/ICP3
INPUT
–
Table 41
71.
relates the alternate functions of Port E to the overriding signals shown in
PE6/INT6/T3
0
0
0
0
0
0
INT6 ENABLE
1
INT7 INPUT/T3
INPUT
–
PE5/INT5/OC3C
0
0
0
0
OC3C ENABLE
OC3C
INT5 ENABLE
1
INT5 INPUT
–
PE4/INT4/OC3B
0
0
0
0
OC3B ENABLE
OC3B
INT4 ENABLE
1
INT4 INPUT
–
ATmega64(L)
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