ATMEGA64-16AI Atmel, ATMEGA64-16AI Datasheet - Page 244

• Manufacturer Part Number: ATMEGA64-16AI
• Description: IC AVR MCU 64K 16MHZ IND 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2490Q–AVR–06/10
• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
sions. For a complete description of this bit, see
page
• Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits
The value of these bits selects which combination of analog inputs are connected to the ADC.
These bits also select the gain for the differential channels. See
are changed during a conversion, the change will not go in effect until this conversion is
complete (ADIF in ADCSRA is set).
Table 98. Input Channel and Gain Selections
MUX4..0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
246.
Single Ended Input
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
N/A
Positive Differential
Input
N/A
ADC0
ADC1
ADC0
ADC1
ADC2
ADC3
ADC2
ADC3
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC0
ADC1
“ADCL and ADCH – The ADC Data Register” on
Negative Differential
Input
ADC0
ADC0
ADC0
ADC0
ADC2
ADC2
ADC2
ADC2
ADC1
ADC1
ADC1
ADC1
ADC1
ADC1
ADC1
ADC1
ADC2
ADC2
Table 98
ATmega64(L)
for details. If these bits
Gain
10x
10x
200x
200x
10x
10x
200x
200x
1x
1x
1x
1x
1x
1x
1x
1x
1x
1x
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