ATMEGA323-8AC Atmel, ATMEGA323-8AC Datasheet - Page 33

• Manufacturer Part Number: ATMEGA323-8AC
• Description: IC AVR MCU 32K 8MHZ COM 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA323-8AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA3238AC

The General Interrupt Control
Register – GICR
1457G–AVR–09/03
l
• Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is activated. The Interrupt Sense Control1 bits 1/0 (ISC11 and
ISC10) in the MCU general Control Register (MCUCR) define whether the external
interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity
on the pin will cause an interrupt request even if INT1 is configured as an output. The
corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Inter-
rupt Vector. See also “External Interrupts” on page 37.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is activated. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the MCU general Control Register (MCUCR) define whether the external
interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on
the pin will cause an interrupt request even if INT0 is configured as an output. The corre-
sponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt
Vector. See also “External Interrupts” on page 37.
• Bit 5 – INT2: External Interrupt Request 2 Enable
When the INT2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is activated. The Interrupt Sense Control2 bit (ISC02) in the
MCU Control and Status Register (MCUCSR) defines whether the external interrupt is
activated on rising or falling edge of the INT2 pin. Activity on the pin will cause an inter-
rupt request even if INT2 is configured as an output. The corresponding interrupt of
External Interrupt Request 2 is executed from the INT2 Interrupt Vector. See also
“External Interrupts” on page 37.
• Bits 4..2 – Res: Reserved Bits
These bits are reserved bits in the ATmega323 and always read as zero.
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the
Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the begin-
ning of the Boot Loader section of the Flash. The actual address to the start of the Boot
Flash section is determined by the BOOTSZ Fuses. Refer to the section “Boot Loader
Support” on page 177 for details. To avoid unintentional changes of Interrupt Vector
tables, a special write procedure must be followed to change the IVSEL bit:
1. Set the Interrupt Vector Change Enable (IVCE) bit.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will be automatically disabled while this sequence is executed. Interrupts are
disabled in the cycle IVCE is set, and they remain disabled until after the instruction fol-
lowing the write to IVSEL. If IVSEL is not written, interrupts remain disabled in four
cycles. The I-flag in the Status Register is unaffected by the automatic disabling.
Bit
$3B ($5B)
Read/Write
Initial Value
INT1
R/W
7
0
INT0
R/W
6
0
INT2
R/W
5
0
R
4
–
0
R
3
–
0
R
–
2
0
ATmega323(L)
IVSEL
R/W
1
0
IVCE
R/W
0
0
GICR
33