ATMEGA323-8AC Atmel, ATMEGA323-8AC Datasheet - Page 31
![IC AVR MCU 32K 8MHZ COM 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA323-8AC
Manufacturer Part Number
ATMEGA323-8AC
Description
IC AVR MCU 32K 8MHZ COM 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA323L-4PC.pdf
(247 pages)
Specifications of ATMEGA323-8AC
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA3238AC
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Internal Voltage Reference
1457G–AVR–09/03
• Bit 6 – ISC2: Interrupt Sense Control 2
The asynchronous external interrupt 2 is activated by the external pin INT2 if the SREG
I-flag and the corresponding interrupt mask in the GICR are set. If ISC2 is cleared
(zero), a falling edge on INT2 activates the interrupt. If ISC2 is set (one) a rising edge on
INT2 activates the interrupt. Edges on INT2 are registered asynchronously. Pulses on
INT2 wider than 50 ns will generate an interrupt. Shorter pulses are not guaranteed to
generate an interrupt. When changing the ISC2 bit, an interrupt can occur. Therefore, it
is recommended to first disable INT2 by clearing its Interrupt Enable bit in the GICR
Register. Then, the ISC2 bit can be changed. Finally, the INT2 Interrupt Flag should be
cleared by writing a logical one to its Interrupt Flag bit in the GIFR Register before the
interrupt is re-enabled.
• Bit 5 – Res: Reserved Bit
This bit is a reserved bit in the ATmega323 and always reads as zero.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register
selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or
by writing a logic zero to the flag.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to
the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and
then reset the MCUCSR as early as possible in the program. If the register is cleared
before another reset occurs, the source of the reset can be found by examining the
Reset Flags.
ATmega323 features an internal bandgap reference with a nominal voltage of 1.22V.
This reference is used for Brown-out Detection, and it can be used as an input to the
Analog Comparator or the ADC. The 2.56V reference to the ADC is generated from the
internal bandgap reference.
ATmega323(L)
31
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