ATMEGA323-8AC Atmel, ATMEGA323-8AC Datasheet - Page 20

• Manufacturer Part Number: ATMEGA323-8AC
• Description: IC AVR MCU 32K 8MHZ COM 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA323-8AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA3238AC

20
ATmega323(L)
Table 2. ATmega323 I/O Space (Continued)
Notes:
All ATmega323 I/Os and peripherals are placed in the I/O space. The I/O locations are
accessed by the IN and OUT instructions, transferring data between the 32 general pur-
pose working registers and the I/O space. I/O Registers within the address range $00 -
$1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
value of single bits can be checked by using the SBIS and SBIC instructions. Refer to
the instruction set chapter for more details. When using the I/O specific commands IN
and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O Registers as
SRAM, $20 must be added to these addresses. All I/O Register addresses throughout
this document are shown with the SRAM address in parentheses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O Memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI
and SBI instructions will operate on all bits in the I/O Register, writing a one back into
any flag read as set, thus clearing the flag. The CBI and SBI instructions work with reg-
isters $00 to $1F only.
The I/O and Peripherals Control Registers are explained in the following sections.
I/O Address (SRAM
Address)
$12 ($32)
$11 ($31)
$10 ($30)
$0F ($2F)
$0E ($2E)
$0D ($2D)
$0C ($2C)
$0B ($2B)
$0A ($2A)
$09 ($29)
$08 ($28)
$07 ($27)
$06 ($26)
$05 ($25)
$04 ($24)
$03 ($23)
$02 ($22)
$01 ($21)
$00 ($20)
1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always
2. Refer to the USART description for details on how to access UBRRH and UCSRC.
accessed on this address. Refer to the debugger specific documentation for details
on how to use the OCDR Register.
Name
PORTD
DDRD
PIND
SPDR
SPSR
SPCR
UDR
UCSRA
UCSRB
UBRRL
ACSR
ADMUX
ADCSR
ADCH
ADCL
TWDR
TWAR
TWSR
TWBR
Data Register, Port D
Input Pins, Port D
SPI I/O Data Register
SPI Status Register
SPI Control Register
USART Control and Status Register A
USART Control and Status Register B
USART Baud Rate Register Low Byte
Analog Comparator Control and Status Register
ADC Control and Status Register
Two-wire Serial Interface Data Register
Two-wire Serial Interface (Slave) Address Register
Two-wire Serial Interface Status Register
Two-wire Serial Interface Bit Rate Register
Function
Data Direction Register, Port D
USART I/O Data Register
ADC Multiplexer Select Register
ADC Data Register High
ADC Data Register Low
1457G–AVR–09/03