ATMEGA323-8AC Atmel, ATMEGA323-8AC Datasheet - Page 239

• Manufacturer Part Number: ATMEGA323-8AC
• Description: IC AVR MCU 32K 8MHZ COM 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA323-8AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA3238AC

Errata for ATmega323
Rev. B
1457G–AVR–09/03
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7. Interrupts Abort TWI Power-down
6. TWI Master Does not Accept Spikes on Bus Lines
5. TWCR Write Operation Ignored when Immediately Repeated
4. PWM not Phase Correct
Interrupts Abort TWI Power-down
TWI Master Does not Accept Spikes on Bus Lines
TWCR Write Operations Ignored when Immediately Repeated
PWM not Phase Correct
TWI is Speed Limited in Slave Mode
Problems with UBRR Settings
Missing OverRun Flag and Fake Frame Error in USART
TWI Power-down operation may wake up by other interrupts. If an interrupt (e.g.,
INT0) occurs during TWI Power-down address watch and wakes up the CPU, the
TWI aborts operation and returns to its idle state.
If the interrupt occurs in the middle of a Power-down Address Match (i.e., during
reading of a slave address), the received address will be lost and the Slave will not
return an ACN.
Problem Fix/Workaround
Ensure that the TWI Address Match is the only enabled interrupt when entering
Power-down.
The Master can handle this by resending the request if NACH is received.
When the part operates as Master, and the bus is idle (SDA = 1; SCL = 1), generat-
ing a short spike on SDA (SDA = 0 for a short interval), no interrupt is generated,
and the status code is still $F8 (idle). But when the software initiates a new start
condition and clears TWINT, nothing happens on SDA or SCL, and TWINT is never
set again.
Problem Fix/Workaround
Either of the following:
1. Ensure no spikes occur on SDA or SCL lines.
2. Generate a valid START condition followed by a STOP condition on the bus.
3. In a Single-master system, the user should write the TWSTO bit immediately
Repeated write to TWCR must be delayed. If a write operation to TWCR is immedi-
ately followed by another write operation to TWCR, the first write operation may be
ignored.
Problem Fix/Workaround
Ensure at least one instruction (e.g., NOP) is executed between two writes to
TWCR.
In phase-correct PWM mode, a change from OCRx = TOP to anything less than
TOP does not change the OCx output. This gives a phase error in the following
period.
Problem Fix/Workaround
Make sure this issue is not harmful to the application.
This provokes a bus error reported as a TWI interrupt with status code $00.
before writing the TWSTA bit.
ATmega323(L)
239