ATMEGA323-8AC Atmel, ATMEGA323-8AC Datasheet - Page 161

• Manufacturer Part Number: ATMEGA323-8AC
• Description: IC AVR MCU 32K 8MHZ COM 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA323-8AC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA3238AC

Using the Boundary-
Scan Chain
Using the On-chip Debug
System
1457G–AVR–09/03
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As shown in the state diagram, the Run-Test/Idle state need not be entered between
selecting JTAG instruction and using Data Registers, and some JTAG instructions may
select certain functions to be performed in the Run-Test/Idle, making it unsuitable as an
Idle state.
Note:
For detailed information on the JTAG specification, refer to the literature listed in “Bibli-
ography” on page 163.
A complete description of the Boundary-Scan capabilities are given in the section “IEEE
1149.1 (JTAG) Boundary-Scan” on page 164.
As shown in Figure 85, the hardware support for On-chip Debugging consists mainly of
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All read or modify/write operations needed for implementing the Debugger are done by
applying AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the
result to an I/O Memory mapped location which is part of the communication interface
between the CPU and the JTAG system.
The Break Point Unit implements Break on Change of Program Flow, Single Step
Break, two Program memory Break Points, and two combined Break Points. Together,
the 4 Break Points can be configured as either:
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A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Spe-
cific JTAG Instructions” on page 162. Note that Atmel supports the On-chip Debug
system with the AVR Studio front-end software for PCs. The details on hardware imple-
Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction
is latched onto the parallel output from the Shift Register path in the Update-IR
state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the
state machine.
At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the
Shift Data Register – Shift-DR state. While TMS is low, upload the selected Data
Register (selected by the present JTAG instruction in the JTAG Instruction Register)
from the TDI input at the rising edge of TCK. At the same time, the parallel inputs to
the Data Register captured in the Capture-DR state shifts out on the TDO pin.
Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected
Data Register has a latched parallel-output, the latching takes place in the Update-
DR state. The Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating
the state machine.
A scan chain on the interface between the internal AVR CPU and the internal
peripheral units.
Break Point unit.
Communication interface between the CPU and JTAG system.
4 single Program memory Break Points
3 Single Program memory Break Point + 1 single Data memory Break Point
2 single Program memory Break Points + 2 single Data memory Break Points
2 single Program memory Break Points + 1 Program memory Break Point with mask
(‘range Break Point’)
2 single Program memory Break Points + 1 Data memory Break Point with mask
(‘range Break Point’)
Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can
always be entered by holding TMS high for 5 TCK clock periods.
ATmega323(L)
161