UPD70F3744GJ-GAE-AX Renesas Electronics America, UPD70F3744GJ-GAE-AX Datasheet - Page 903

• Manufacturer Part Number: UPD70F3744GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3744GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 128
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JJ3
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
CRC
function
Regulator Regulator
Flash
memory
On-chip
debug
function
Function
CRCD register
FLMD1 pin
PG-FP4
FA-144GJ-UEN-A
Selection of
communication
mode
FLMD1 pin
FLMD0 pin
OCDM register
Cautions (DUC)
Details of
Function
Accessing the CRCD register is prohibited in the following statuses. For details,
refer to 3.4.9 (2) Accessing specific on-chip peripheral I/O registers.
•
•
Use the regulator with a setting of V
Connect the FLMD1 pin to the flash programmer or connect to a GND via a pull-
down resistor on the board.
Wire these pins as shown in Figure 27-6, or connect then to GND via pull-down
resistor on board.
Clock cannot be supplied via the CLK pin of the flash programmer. Create an
oscillator on board and supply the clock.
Be sure to connect the REGC pin to GND via a 4.7
capacitor.
A clock cannot be supplied from the CLK pin of the flash programmer. Create an
oscillator on the board and supply the clock from that oscillator.
Wire the FLMD1 pin as shown below, or connect it to GND on board via a pull-
down resistor.
Supply a clock by creating an oscillator on the flash writing adapter (enclosed by
the broken lines).
Do not input a high level to the DRST pin.
When UARTA0 is selected, the receive clock is calculated based on the reset
command sent from the dedicated flash programmer after receiving the FLMD0
pulse.
If the V
writing and immediately after reset, isolate this signal.
Make sure that the FLMD0 pin is at 0 V when reset is released.
When using the DDI, DDO, DCK, and DMS pins not as on-chip debug pins but as
port pins after external reset, any of the following actions must be taken.
• Input a low level to the P05/INTP2/DRST pin.
• Set the OCDM0 bit. In this case, take the following actions.
The DRST pin has an on-chip pull-down resistor. This resistor is disconnected
when the OCDM0 flag is cleared to 0.
If a reset signal is input (from the target system or a reset signal from an internal
reset source) during RUN (program execution), the break function may
malfunction.
Even if the reset signal is masked by the mask function, the I/O buffer (port pin)
may be reset if a reset signal is input from a pin.
Pin reset during a break is masked and the CPU and peripheral I/O are not reset.
If pin reset or internal reset is generated as soon as the flash memory is rewritten
by DMM or read by the RAM monitor function while the user program is being
executed, the CPU and peripheral I/O may not be correctly reset.
When the CPU operates with the subclock and the main clock oscillation is
stopped
When the CPU operates with the internal oscillation clock
<1> Clear the OCDM0 bit to 0.
<2> Fix the P05/INTP2/DRST pin to low level until <1> is completed.
DD
signal is input to the FLMD1 pin from another device during on-board
DD
Cautions
= EV
DD
= AV
APPENDIX E LIST OF CAUTIONS
REF0
μ
F (recommended value)
= AV
REF1
.
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