UPD70F3744GJ-GAE-AX Renesas Electronics America, UPD70F3744GJ-GAE-AX Datasheet - Page 13

• Manufacturer Part Number: UPD70F3744GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3744GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 128
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) ................................................................... 629
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION............................................... 652
17.7
17.8
17.9
17.10 Error Detection...................................................................................................................... 605
17.11 Extension Code..................................................................................................................... 605
17.12 Arbitration ............................................................................................................................. 606
17.13 Wakeup Function.................................................................................................................. 607
17.14 Communication Reservation............................................................................................... 608
17.15 Cautions ................................................................................................................................ 613
17.16 Communication Operations................................................................................................. 614
17.17 Timing of Data Communication .......................................................................................... 622
18.1
18.2
18.3
18.4
18.5
18.6
18.7
18.8
18.9
18.10 DMA Abort Factors ............................................................................................................... 642
18.11 End of DMA Transfer ............................................................................................................ 642
18.12 Operation Timing .................................................................................................................. 642
18.13 Cautions ................................................................................................................................ 647
19.1
19.2
19.3
17.6.5
17.6.6
17.6.7
I
17.7.1
17.7.2
17.7.3
17.7.4
17.7.5
17.7.6
Interrupt Request Signal (INTIICn) Generation Timing and Wait Control....................... 603
Address Match Detection Method ...................................................................................... 605
17.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) .......................608
17.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1).......................612
17.16.1 Master operation in single master system ................................................................................615
17.16.2 Master operation in multimaster system ...................................................................................615
17.16.3 Slave operation ........................................................................................................................619
Features................................................................................................................................. 629
Configuration ........................................................................................................................ 630
Registers ............................................................................................................................... 631
Transfer Targets ................................................................................................................... 638
Transfer Modes ..................................................................................................................... 639
Transfer Types ...................................................................................................................... 639
DMA Channel Priorities........................................................................................................ 640
Time Related to DMA Transfer ............................................................................................ 640
DMA Transfer Start Factors................................................................................................. 641
Features................................................................................................................................. 652
Non-Maskable Interrupts ..................................................................................................... 656
19.2.1
19.2.2
19.2.3
Maskable Interrupts.............................................................................................................. 661
19.3.1
19.3.2
2
C Interrupt Request Signals (INTIICn) .............................................................................. 583
Stop condition ..........................................................................................................................579
Wait state.................................................................................................................................580
Wait state cancellation method ................................................................................................582
Master device operation...........................................................................................................583
Slave device operation (when receiving slave address data (address match)) ........................586
Slave device operation (when receiving extension code).........................................................590
Operation without communication............................................................................................594
Arbitration loss operation (operation as slave after arbitration loss).........................................594
Operation when arbitration loss occurs (no communication after arbitration loss) ...................596
Operation .................................................................................................................................658
Restore ....................................................................................................................................659
NP flag .....................................................................................................................................660
Operation .................................................................................................................................661
Restore ....................................................................................................................................663