SAB-C161O-LM 3V HA Infineon Technologies, SAB-C161O-LM 3V HA Datasheet - Page 49

• Manufacturer Part Number: SAB-C161O-LM 3V HA
• Description: IC MICROCONTROLLER 16BIT MQFP80
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAB-C161O-LM 3V HA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-SQFP
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: 1xASC, 1xSSC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 63
• Number Of Timers: 5
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Packages: PG-MQFP-80
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 2.0 KByte
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: B161OLM3VHAXT; SABC161OLM3VHAXT; SP000011588

Multiplexed Bus (Reduced Supply Voltage Range) (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
Parameter
Data float after RD
Data valid to WR
Data hold after WR
ALE rising edge after RD,
WR
Address hold after RD,
WR
ALE falling edge to CS
CS low to Valid Data In
CS hold after RD, WR
ALE fall. edge to RdCS,
WrCS (with RW delay)
ALE fall. edge to RdCS,
WrCS (no RW delay)
Address float after RdCS,
WrCS (with RW delay)
Address float after RdCS,
WrCS (no RW delay)
RdCS to Valid Data In
(with RW delay)
RdCS to Valid Data In
(no RW delay)
RdCS, WrCS Low Time
(with RW delay)
RdCS, WrCS Low Time
(no RW delay)
Data Sheet
1)
1)
1)
t
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
A
19
22
23
25
27
38
39
40
42
43
44
45
46
47
48
49
+
t
CC 24 +
CC 36 +
CC 36 +
CC 36 +
CC -8 -
CC 57 +
CC 19 +
CC -6 +
CC –
CC –
CC 38 +
CC 63 +
SR –
SR –
SR –
SR –
C
+
t
F
min.
Max. CPU Clock
(150 ns at 20 MHz CPU clock without waitstates)
t
= 20 MHz
t
A
t
t
t
t
t
t
t
t
45
A
C
F
F
F
F
A
C
C
max.
36 +
–
–
–
–
10 -
47+
+ 2
–
–
–
0
25
20 +
45 +
–
–
t
A
t
t
t
C
t
t
A
F
C
C
1 / 2TCL = 1 to 20 MHz
min.
–
2TCL - 26
+
2TCL - 14
+
2TCL - 14
+
2TCL - 14
+
-8 -
–
3TCL - 18
+
TCL - 6
+
-6
+
–
–
–
–
2TCL - 12
+
3TCL - 12
+
Variable CPU Clock
t
t
t
t
t
t
t
t
t
C
F
F
F
F
A
A
C
C
t
A
max.
2TCL - 14
+
–
–
–
–
10 -
3TCL - 28
+
–
–
–
0
TCL
2TCL - 30
+
3TCL - 30
+
–
–
t
t
t
t
F
C
C
C
t
+ 2
V2.0, 2001-01
A
t
A
C161O
C161K
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns