SAB-C161O-LM 3V HA Infineon Technologies, SAB-C161O-LM 3V HA Datasheet - Page 16

• Manufacturer Part Number: SAB-C161O-LM 3V HA
• Description: IC MICROCONTROLLER 16BIT MQFP80
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAB-C161O-LM 3V HA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-SQFP
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: 1xASC, 1xSSC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 63
• Number Of Timers: 5
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Packages: PG-MQFP-80
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 2.0 KByte
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: B161OLM3VHAXT; SABC161OLM3VHAXT; SP000011588

Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C161K/O’s instructions can be
executed in just one machine cycle which requires 80 ns at 25 MHz CPU clock. For
example, shift and rotate instructions are always processed during one machine cycle
independent of the number of bits to be shifted. All multiple-cycle instructions have been
optimized so that they can be executed very fast as well: branches in 2 cycles, a 16
bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline
optimization, the so-called ‘Jump Cache’, allows reducing the execution time of
repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
Figure 4
Data Sheet
ROM
CPU Block Diagram
32
Data Page Ptr.
Exec. Unit
Instr. Reg.
SYSCON
Instr. Ptr.
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
STKUN
STKOV
PSW
SP
Pipeline
4-Stage
Barrel - Shifter
Bit-Mask Gen
Code Seg. Ptr.
Mul/Div-HW
Context Ptr.
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
ALU
MDH
CPU
MDL
12
(16-bit)
Registers
Purpose
General
R15
R0
16
16
V2.0, 2001-01
Internal
RAM
R15
R0
C161O
C161K
MCB02147
16