UPD78F9234MC-5A4-A Renesas Electronics America, UPD78F9234MC-5A4-A Datasheet - Page 409

• Manufacturer Part Number: UPD78F9234MC-5A4-A
• Description: MCU 8BIT 8KB FLASH 30PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9234MC-5A4-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Flash
memory
Function
Self
programming
function
FLPMC: Flash
programming
mode control
register
PFCMD: Flash
protect command
register
PFS: Flash
status register
FLAPH and
FLAPL: Flash
address pointers
H and L
FLAPHC and
FLAPLC: Flash
address pointer
H compare
register and flash
address pointer L
compare register
Details of
Function
Since the security function set via on-board/off-board programming is disabled
in self programming mode, the self programming command can be executed
regardless of the security function setting. To disable write or erase
processing during self programming, set the protect byte.
Be sure to clear bits 5 to 7 of flash address pointer H (FLAPH) and flash
address pointer H compare register (FLAPHC) to 0 before executing the self
programming command. If the self programming command is executed with
these bits set to 1, the device may malfunction.
Clear the value of the FLCMD register to 00H immediately before setting to
self programming mode and normal mode.
Cautions in the case of setting the self programming mode, refer to 19.8.2
Cautions on self programming function.
Set the CPU clock beforehand so that it is 1 MHz or higher during self
programming.
Execute self programming after executing the NOP and HALT instructions
immediately after executing a specific sequence to set self programming
mode. At this time, the HALT instruction is automatically released after 10
(MAX.) + 2 CPU clocks (f
If the clock of the oscillator or an external clock is selected as the system
clock, execute the NOP and HALT instructions immediately after executing a
specific sequence to set self programming mode, wait for 8
the HALT status, and then execute self programming.
Clear the value of the FLCMD register to 00H immediately before setting to
self programming mode and normal mode.
Interrupt servicing cannot be executed in self programming mode. Disable
interrupt servicing (by executing the DI instruction while MK0 and MK1 = FFH)
between the points before executing the specific sequence that sets self
programming mode and after executing the specific sequence that changes
the mode to the normal mode.
Check FPRERR using a 1-bit memory manipulation instruction.
Be sure to clear bits 5 to 7 of FLAPH and FLAPHC to 0 before executing the
self programming command. If the self programming command is executed
with these bits set to 1, the device may malfunction.
Be sure to clear bits 5 to 7 of FLAPH and FLAPHC to 0 before executing the
self programming command. If the self programming command is executed
with these bits set to 1, the device may malfunction.
Set the number of the block subject to a block erase, verify, or blank check
(same value as FLAPH) to FLAPHC.
Clear FLAPLC to 00H when a block erase is performed, and FFH when a
blank check is performed.
APPENDIX D LIST OF CAUTIONS
User’s Manual U17446EJ5V0UD
CPU
).
Cautions
μ
s after releasing
μ
s
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