UPD78F9234MC-5A4-A Renesas Electronics America, UPD78F9234MC-5A4-A Datasheet - Page 154
UPD78F9234MC-5A4-A
Manufacturer Part Number
UPD78F9234MC-5A4-A
Description
MCU 8BIT 8KB FLASH 30PIN
Manufacturer
Renesas Electronics America
Series
78K0S/Kx1+r
Datasheet
1.UPD78F9232MC-5A4-A.pdf
(419 pages)
Specifications of UPD78F9234MC-5A4-A
Core Processor
78K0S
Core Size
8-Bit
Speed
10MHz
Connectivity
LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F9234MC-5A4-A
Manufacturer:
MAXIM
Quantity:
1 001
Part Number:
UPD78F9234MC-5A4-A
Manufacturer:
NEC
Quantity:
20 000
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Watchdog timer clock
source
Operation after reset
Operation mode
selection
Features
Notes 1.
Remarks 1. f
2.
2. f
As long as power is being supplied, low-speed internal oscillator cannot be stopped (except in the reset
period).
The conditions under which clock supply to the watchdog timer is stopped differ depending on the
clock source of the watchdog timer.
<1> If the clock source is f
<2> If the clock source is f
RL
X
: System clock oscillation frequency
: Low-speed internal oscillation clock frequency
conditions.
conditions.
Table 9-2. Option Byte Setting and Watchdog Timer Operation Mode
When f
In HALT/STOP mode
During oscillation stabilization time
If the CPU clock is f
In HALT/STOP mode
Fixed to f
Operation starts with the maximum interval (2
The interval can be changed only once.
The watchdog timer cannot be stopped.
Low-Speed Internal Oscillator Cannot Be Stopped
X
is stopped
RL
Note 1
.
CHAPTER 9 WATCHDOG TIMER
X
and if f
RL
X
User’s Manual U17446EJ5V0UD
, clock supply to the watchdog timer is stopped under the following
, clock supply to the watchdog timer is stopped under the following
RL
is stopped by software before execution of the STOP instruction
Option Byte Setting
18
/f
RL
). Operation starts with the maximum interval
(2
The clock selection/interval can be changed only
once.
The watchdog timer can be stopped
18
Low-Speed Internal Oscillator Can Be Stopped
Selectable by software (f
When reset is released: f
/f
RL
).
by Software
X
RL
, f
RL
or stopped)
Note 2
.
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