D64F3437TFLH16V Renesas Electronics America, D64F3437TFLH16V Datasheet - Page 292

• Manufacturer Part Number: D64F3437TFLH16V
• Description: MCU 5V 60K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of D64F3437TFLH16V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.3.2
In asynchronous mode, each transmitted or received character is individually synchronized by
framing it with a start bit and stop bit.
Full duplex data transfer is possible because the SCI has independent transmit and receive
sections. Double buffering in both sections enables the SCI to be programmed for continuous data
transfer.
Figure 12.2 shows the general format of one character sent or received in asynchronous mode. The
communication channel is normally held in the mark state (high). Character transmission or
reception starts with a transition to the space state (low).
The first bit transmitted or received is the start bit (low). It is followed by the data bits, in which
the least significant bit (LSB) comes first. The data bits are followed by the parity or
multiprocessor bit, if present, then the stop bit or bits (high) confirming the end of the frame.
In receiving, the SCI synchronizes on the falling edge of the start bit, and samples each bit at the
center of the bit (at the 8th cycle of the internal serial clock, which runs at 16 times the bit rate).
260
Start bit
1 bit
Asynchronous Mode
D0
Figure 12.2 Data Format in Asynchronous Mode
One unit of data (one character or frame)
D1
7 or 8 bits
Dn
cessor bit
0 or 1 bit
multipro-
Parity or
1 or 2 bits
Stop bit
Idle state
(mark)