D64F3437TFLH16V Renesas Electronics America, D64F3437TFLH16V Datasheet - Page 102

• Manufacturer Part Number: D64F3437TFLH16V
• Description: MCU 5V 60K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of D64F3437TFLH16V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.3.2
The interrupt-related registers are the system control register (SYSCR), IRQ sense control register
(ISCR), IRQ enable register (IER), and keyboard matrix interrupt mask registers (KMIMR and
KMIMRA).
Table 4.3
Name
System control register
IRQ sense control register
IRQ enable register
Keyboard matrix interrupt mask register
Keyboard matrix interrupt mask register A
System Control Register (SYSCR)
The valid edge on the NMI line is controlled by bit 2 (NMIEG) in the system control register.
Bit 2—NMI Edge (NMIEG): Determines whether a nonmaskable interrupt is generated on the
falling or rising edge of the NMI input signal.
Bit 2: NMIEG
0
1
See section 3.2, System Control Register, for information on the other SYSCR bits.
IRQ Sense Control Register (ISCR)
70
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Interrupt-Related Registers
Registers Read by Interrupt Controller
IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
SSBY
R/W
R/W
Description
An interrupt is generated on the falling edge of NMI.
An interrupt is generated on the rising edge of NMI.
7
0
7
0
STS2
R/W
R/W
6
0
6
0
STS1
R/W
R/W
5
0
5
0
Abbreviation
SYSCR
ISCR
IER
KMIMR
KMIMRA
STS0
R/W
R/W
4
0
4
0
XRST
R/W
3
1
R
3
0
Read/Write
R/W
R/W
R/W
R/W
R/W
NMIEG
R/W
R/W
2
0
2
0
R/W
R/W
HIE
Address
H'FFC4
H'FFC6
H'FFC7
H'FFF1
H'FFF3
1
0
1
0
(Initial state)
RAME
R/W
R/W
0
1
0
0