D64F3437TFLH16V Renesas Electronics America, D64F3437TFLH16V Datasheet - Page 149
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D64F3437TFLH16V
Manufacturer Part Number
D64F3437TFLH16V
Description
MCU 5V 60K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Datasheet
1.HD64F3437STF16V.pdf
(755 pages)
Specifications of D64F3437TFLH16V
Core Processor
H8/300
Core Size
8-Bit
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D64F3437TFLH16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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7.4.2
Table 7.6 summarizes the port 3 registers.
Table 7.6
Name
Port 3 data direction register
Port 3 data register
Port 3 input pull-up control
register
Port 3 Data Direction Register (P3DDR)
P3DDR is an 8-bit register that controls the input/output direction of each pin in port 3. P3DDR is
a write-only register. Read data is invalid. If read, all bits always read 1.
Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded
mode with on-chip ROM enabled), the input/output directions designated by P3DDR are ignored.
Port 3 automatically consists of the input/output pins of the 8-bit data bus (D
The data bus is in the high-impedance state during reset, and during hardware and software
standby.
Mode 3: A pin in port 3 is used for general output if the corresponding P3DDR bit is set to 1, and
for general input if this bit is cleared to 0. P3DDR is initialized to H'00 by a reset and in hardware
standby mode. In software standby mode it retains its existing values, so if a transition to software
standby mode occurs while a P3DDR bit is set to 1, the corresponding pin remains in the output
state.
Bit
Initial value
Read/Write
Register Configuration and Descriptions
Port 3 Registers
P3
7
W
7
DDR P3
0
6
W
6
DDR P3
0
Abbreviation
P3DDR
P3DR
P3PCR
5
W
5
DDR P3
0
Read/Write
W
R/W
R/W
4
W
4
DDR P3
0
3
W
3
DDR P3
0
Initial Value
H'00
H'00
H'00
2
W
2
DDR P3
0
7
to D
1
0
W
1
DDR P3
0
).
Address
H'FFB4
H'FFB6
H'FFAE
0
W
0
DDR
0
117
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