D64F3437TFLH16V Renesas Electronics America, D64F3437TFLH16V Datasheet - Page 192

• Manufacturer Part Number: D64F3437TFLH16V
• Description: MCU 5V 60K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of D64F3437TFLH16V

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.2.3
There are four input capture registers A to D, each of which is a 16-bit read-only register.
When the rising or falling edge of the signal at an input capture pin (FTIA to FTID) is detected,
the current FRC value is copied to the corresponding input capture register (ICRA to ICRD).* At
the same time, the corresponding input capture flag (ICFA to ICFD) in the timer control/status
register (TCSR) is set to 1. The input capture edge is selected by the input edge select bits
(IEDGA to IEDGD) in the timer control register (TCR).
Note: * The FRC contents are transferred to the input capture register regardless of the value of the
Input capture can be buffered by using the input capture registers in pairs. When the BUFEA bit in
TCR is set to 1, ICRC is used as a buffer register for ICRA as shown in figure 8.2. When an FTIA
input is received, the old ICRA contents are moved into ICRC, and the new FRC count is copied
into ICRA.
160
BUFEA:
IEDGA:
IEDGC:
ICRC:
ICRA:
FRC:
Bit
Initial value
Read/Write
input capture flag (ICFA/B/C/D).
Input Capture Registers A to D (ICRA to ICRD)
FTIA
Buffer enable A
Input edge select A
Input edge select C
Input capture register C
Input capture register A
Free-running counter
15
R
0
14
R
0
Figure 8.2 Input Capture Buffering (Example)
generating circuit
Edge detect and
IEDGA
13
capture signal
R
0
BUFEA
12
R
0
IEDGC
ICRC
11
R
0
10
R
0
R
9
0
R
8
0
ICRA
R
7
0
R
6
0
R
5
0
R
4
0
R
3
0
FRC
R
2
0
R
1
0
R
0
0