HD6473308RCP10V Renesas Electronics America, HD6473308RCP10V Datasheet - Page 149
HD6473308RCP10V
Manufacturer Part Number
HD6473308RCP10V
Description
MCU 5V 16K,PB-FREE 80-PLCC
Manufacturer
Renesas Electronics America
Series
H8® H8/330r
Datasheet
1.HD6473258P10V.pdf
(349 pages)
Specifications of HD6473308RCP10V
Core Size
8-Bit
Program Memory Size
16KB (16K x 8)
Oscillator Type
Internal
Core Processor
H8/300
Speed
10MHz
Number Of I /o
58
Program Memory Type
OTP
Ram Size
512 x 8
Operating Temperature
-20°C ~ 75°C
Package / Case
80-PLCC
No. Of I/o's
58
Ram Memory Size
512Byte
Cpu Speed
10MHz
No. Of Timers
3
No. Of Pwm Channels
2
Digital Ic Case
RoHS Compliant
Controller Family/series
H8/330
Peripherals
ADC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply (vcc/vdd)
-
Eeprom Size
-
Data Converters
-
Peripherals
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6473308RCP10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit 0 – Counter Clear A (CCLRA): This bit selects whether to clear the FRC at compare-match
A (when the FRC and OCRA values match).
Bit 0
CCLRA Description
6.2.6 Timer Control Register (TCR) – H’FF96
Bit
Initial value
Read/Write
The TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input
capture signals, enables the input capture buffer mode, and selects the FRC clock source.
The TCR is initialized to H’00 at a reset and in the standby modes.
Bit 7 – Input Edge Select A (IEDGA): This bit causes input capture A events to be recognized on
the selected edge of the input capture A signal (FTIA).
Bit 7
IEDGA
Bit 6 – Input Edge Select B (IEDGB): This bit causes input capture B events to be recognized on
the selected edge of the input capture B signal (FTIB).
Bit 6
IEDGB
0
1
0
1
0
1
The FRC is not cleared.
The FRC is cleared at compare-match A.
Description
Input capture A events are recognized on the falling edge of FTIA.
Input capture A events are recognized on the rising edge of FTIA.
Description
Input capture B events are recognized on the falling edge of FTIB.
Input capture B events are recognized on the rising edge of FTIB.
IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB
R/W
7
0
R/W
6
0
R/W
5
0
134
R/W
4
0
R/W
3
0
R/W
2
0
CKS1
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
CKS0
R/W
0
0
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