DF2367VTE33 Renesas Electronics America, DF2367VTE33 Datasheet - Page 714
DF2367VTE33
Manufacturer Part Number
DF2367VTE33
Description
IC H8S MCU FLASH 384K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2367VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2367VTE33
HD64F2367VTE33
HD64F2367VTE33
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2367VTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 15 I
Rev.6.00 Mar. 18, 2009 Page 654 of 980
REJ09B0050-0600
No
No
No
Write transmit data in ICDRT
Write transmit data in ICDRT
2
No
No
No
C Bus Interface2 (IIC2) (Option)
Read ACKBR in ICIER
Set MST = 1 and TRS
Read BBSY in ICCRB
Set MST = 1 and TRS
Read TDRE in ICSR
Read TEND in ICSR
Clear TEND in ICSR
Clear STOP in ICSR
Read STOP in ICSR
Clear TDRE in ICSR
Read TEND in ICSR
Write transmit data
Write BBSY = 1
Write BBSY = 0
= 0 in ICCRA
= 1 in ICCRA.
Figure 15.14 Sample Flowchart for Master Transmit Mode
and SCP = 0.
and SCP = 0
ACKBR=0 ?
Final byte?
BBSY=0 ?
TEND=1 ?
TDRE=1 ?
TEND=1 ?
STOP=1 ?
in ICDRT
Transmit
Initialize
mode?
Start
End
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Master receive mode
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Wait for the completion of transmission for the final byte.
[11] Clear TEND flag.
[12] Clear STOP flag.
[13] Stop condition issuance.
[14] Wait for the creation of the stop condition.
[15] Set slave receive mode. Clear TDRE.
and clear TDRE to 0.
and clear TDRE and TEND to 0.
Test the status of the SCL and SDA lines.*
Select master transmit mode.*
Start condition issuance.*
Select transmit data for the first byte (slave address + R/W),
Wait for 1 byte to be transmitted.
Test the acknowledge bit, transferred from the specified slave device.
Set transmit data for the second and subsequent data (except for the final byte),
Wait for ICDRT empty.
Set the final byte of transmit data, and clear TDRE and TEND to 0.
Note: * Ensure that no interrupts occur between
when BBSY is cleared to 0 and start condition [3].
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