DF2367VTE33 Renesas Electronics America, DF2367VTE33 Datasheet - Page 618

• Manufacturer Part Number: DF2367VTE33
• Description: IC H8S MCU FLASH 384K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VTE33; HD64F2367VTE33

Section 14 Serial Communication Interface (SCI, IrDA)
Note:
Rev.6.00 Mar. 18, 2009 Page 558 of 980
REJ09B0050-0600
Bit
3
2
1
0
*
Bit Name
PER
TEND
MPB
MPBT
Only 0 can be written, to clear the flag. Alternately, use the bit clear instruction to clear
the flag.
Initial Value
0
1
0
0
R/W
R/(W) *
R
R
R/W
Description
Parity Error
Indicates that a parity error occurred while
receiving in asynchronous mode and the
reception has ended abnormally.
[Setting condition]
When a parity error is detected during reception
If a parity error occurs, the receive data is
transferred to RDR but the RDRF flag is not set.
Also, subsequent serial reception cannot be
continued while the PER flag is set to 1. In
clocked synchronous mode, serial transmission
cannot be continued, either.
[Clearing condition]
When 0 is written to PER after reading PER = 1
The PER flag is not affected and retains its
previous state when the RE bit in SCR is cleared
to 0.
Transmit End
[Setting conditions]
•
•
[Clearing conditions]
•
•
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive
data. When the RE bit in SCR is cleared to 0 its
previous state is retained.
Multiprocessor Bit Transfer
MPBT sets the multiprocessor bit to be added to
the transmit data.
When the TE bit in SCR is 0
When TDRE = 1 at transmission of the last bit
of a 1-byte serial transmit character
When 0 is written to TDRE after reading
TDRE = 1
When the DMAC or DTC is activated by a TXI
interrupt and writes data to TDR