R4F24569NVFQV Renesas Electronics America, R4F24569NVFQV Datasheet - Page 745
![MCU 256KB FLASH 64K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R4F24569NVFQV
Manufacturer Part Number
R4F24569NVFQV
Description
MCU 256KB FLASH 64K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24569NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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H8S/2456, H8S/2456R, H8S/2454 Group
11.3.3
TIOR registers control the TGR registers. The TPU has eight TIOR registers, two each for
channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected
by the TMDR setting.
The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is
cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is
cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5
TIORL_0, TIORL_3
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit Name
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
Bit Name
IOD3
IOD2
IOD1
IOD0
IOC3
IOC2
IOC1
IOC0
Timer I/O Control Register (TIOR)
0
0
0
0
0
0
0
0
Initial Value
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
I/O Control B3 to B0
Specify the function of TGRB.
For details, see tables 11.13, 11.15, 11.16, 11.17,
11.19, and 11.20.
I/O Control A3 to A0
Specify the function of TGRA.
For details, see tables 11.21, 11.23, 11.24, 11.25,
11.27, and 11.28.
Description
I/O Control D3 to D0
Specify the function of TGRD.
For details, see tables 11.14 and 11.18.
I/O Control C3 to C0
Specify the function of TGRC.
For details, see tables 11.22 and 11.26.
Section 11 16-Bit Timer Pulse Unit (TPU)
Page 715 of 1392
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