R4F24569NVFQV Renesas Electronics America, R4F24569NVFQV Datasheet - Page 12
![MCU 256KB FLASH 64K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R4F24569NVFQV
Manufacturer Part Number
R4F24569NVFQV
Description
MCU 256KB FLASH 64K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24569NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R4F24569NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
R4F24569NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.4
6.5
6.6
6.7
Page xii of xxx
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10 DRAM Access Control Register (DRACCR)....................................................... 181
6.3.11 Refresh Control Register (REFCR) ...................................................................... 184
6.3.12 Refresh Timer Counter (RTCNT)......................................................................... 187
6.3.13 Refresh Time Constant Register (RTCOR) .......................................................... 187
Bus Control........................................................................................................................ 188
6.4.1
6.4.2
6.4.3
6.4.4
Basic Bus Interface ............................................................................................................ 194
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
Address/Data Multiplexed I/O Interface............................................................................ 209
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
6.6.7
6.6.8
DRAM Interface ................................................................................................................ 223
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
6.7.6
6.7.7
6.7.8
6.7.9
Area 0 Burst ROM Interface Control Register (BROMCRH)
Area 1 Burst ROM Interface Control Register (BROMCRL) .............................. 169
Bus Control Register (BCR) ................................................................................. 170
Address/Data Multiplexed I/O Control Register (MPXCR) ................................. 172
DRAM Control Register (DRAMCR) .................................................................. 173
Area Division........................................................................................................ 188
Bus Specifications ................................................................................................ 189
Memory Interfaces................................................................................................ 191
Chip Select Signals ............................................................................................... 193
Data Size and Data Alignment.............................................................................. 194
Valid Strobes ........................................................................................................ 196
Basic Timing......................................................................................................... 197
Wait Control ......................................................................................................... 205
Read Strobe (RD) Timing..................................................................................... 206
Extension of Chip Select (CS) Assertion Period................................................... 208
Setting Address/Data Multiplexed I/O Space ....................................................... 209
Address/Data Multiplexing................................................................................... 209
Data Bus ............................................................................................................... 210
Address Hold Signal ............................................................................................. 210
Basic Timing......................................................................................................... 210
Wait Control ......................................................................................................... 219
Read Strobe (RD) Timing..................................................................................... 220
Extension of Chip Select (CS) Assertion Period in Data Cycle............................ 221
Setting DRAM Space............................................................................................ 223
Address Multiplexing ........................................................................................... 224
Data Bus ............................................................................................................... 225
Pins Used for DRAM Interface............................................................................. 226
Basic Timing......................................................................................................... 227
Column Address Output Cycle Control ................................................................ 229
Row Address Output State Control....................................................................... 230
Precharge State Control ........................................................................................ 232
Wait Control ......................................................................................................... 233
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