R4F24569NVFQV Renesas Electronics America, R4F24569NVFQV Datasheet - Page 444

• Manufacturer Part Number: R4F24569NVFQV
• Description: MCU 256KB FLASH 64K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24569NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 EXDMA Controller (EXDMAC)
8.3.4
EDMDR controls EXDMAC operations.
Page 414 of 1392
Bit
15
Bit Name
EDA
EXDMA Mode Control Register (EDMDR)
Initial Value
0
R/W
R/(W)
Description
EXDMA Active
Enables or disables data transfer on the
corresponding channel. When this bit is set to 1,
this indicates that an EXDMA operation is in
progress.
When auto request mode is specified (by bits
MDS1 and MDS0), transfer processing begins
when this bit is set to 1. With external requests,
transfer processing begins when a transfer
request is issued after this bit has been set to 1.
When this bit is cleared to 0 during an EXDMA
operation, transfer is halted. If this bit is cleared to
0 during an EXDMA operation in block transfer
mode, transfer processing is continued for the
currently executing one-block transfer, and the bit
is cleared on completion of the currently executing
one-block transfer.
If an external source that ends (aborts) transfer
occurs, this bit is automatically cleared to 0 and
transfer is terminated. Do not change the
operating mode, transfer method, or other
parameters while this bit is set to 1.
0: Data transfer disabled on corresponding
[Clearing conditions]
•
•
•
•
1: Data transfer enabled on corresponding
Note: The value written in the EDA bit may not
channel
channel
When the specified number of transfers end
When operation is halted by a repeat area
overflow interrupt
When 0 is written to EDA while EDA = 1
(In block transfer mode, write is effective after
end of one-block transfer)
Reset, NMI interrupt, hardware standby mode
be effective immediately.
H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010