R4F24569NVFQV Renesas Electronics America, R4F24569NVFQV Datasheet - Page 451
![MCU 256KB FLASH 64K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R4F24569NVFQV
Manufacturer Part Number
R4F24569NVFQV
Description
MCU 256KB FLASH 64K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24569NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R4F24569NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
R4F24569NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
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H8S/2456, H8S/2456R, H8S/2454 Group
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Bit
7
6
5
Bit Name
DAT1
DAT0
DARIE
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
Destination Address Update Mode
These bits specify incrementing/decrementing of
the transfer destination address (EDDAR). When
an external device with DACK is designated as the
transfer destination in single address mode, the
specification by these bits is ignored.
0x: Fixed
10: Incremented (+1 in byte transfer, +2 in word
11: Decremented (–1 in byte transfer, –2 in word
Destination Address Repeat Interrupt Enable
When this bit is set to 1, in the event of destination
address repeat area overflow the IRF bit is set to 1
and the EDA bit cleared to 0 in EDMDR, and
transfer is terminated. If the EDIE bit in EDMDR is
1 when the IRF bit in EDMDR is set to 1, an
interrupt request is sent to the CPU. When used
together with block transfer mode, a destination
address repeat interrupt is requested at the end of
a block-size transfer. If the EDA bit is set to 1 in
EDMDR for the channel on which transfer is
terminated by a destination address repeat
interrupt, transfer can be resumed from the state
in which it ended. If a destination address repeat
area has not been designated, this bit is ignored.
0: Destination address repeat interrupt is not
1: When destination address repeat area overflow
requested
occurs, the IRF bit in EDMDR is set to 1 and an
interrupt is requested
transfer)
transfer)
Section 8 EXDMA Controller (EXDMAC)
Page 421 of 1392
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