R4F24569NVFQV Renesas Electronics America, R4F24569NVFQV Datasheet - Page 11
![MCU 256KB FLASH 64K 144-LQFP](/photos/28/61/286117/144-lqfp__plqp0144ka-a_sml.jpg)
R4F24569NVFQV
Manufacturer Part Number
R4F24569NVFQV
Description
MCU 256KB FLASH 64K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Specifications of R4F24569NVFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
R4F24569NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
R4F24569NVFQV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 5 Interrupt Controller ............................................................................109
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Section 6 Bus Controller (BSC).........................................................................151
6.1
6.2
6.3
Features.............................................................................................................................. 109
Input/Output Pins............................................................................................................... 111
Register Descriptions ......................................................................................................... 112
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
Interrupt Sources................................................................................................................ 129
5.4.1
5.4.2
Interrupt Exception Handling Vector Table....................................................................... 131
Interrupt Control Modes and Interrupt Operation .............................................................. 138
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
Usage Notes ....................................................................................................................... 147
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
5.7.6
Features.............................................................................................................................. 151
Input/Output Pins............................................................................................................... 154
Register Descriptions ......................................................................................................... 157
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
Interrupt Control Register (INTCR) ..................................................................... 113
Interrupt Priority Registers A to N (IPRA to IPRN)............................................. 114
IRQ Enable Register (IER) ................................................................................... 116
IRQ Sense Control Registers H and L (ISCRH, ISCRL)...................................... 118
IRQ Status Register (ISR)..................................................................................... 124
IRQ Pin Select Register (ITSR)............................................................................ 125
Software Standby Release IRQ Enable Register (SSIER) .................................... 128
External Interrupts ................................................................................................ 129
Internal Interrupts ................................................................................................. 130
Interrupt Control Mode 0...................................................................................... 139
Interrupt Control Mode 2...................................................................................... 141
Interrupt Exception Handling Sequence ............................................................... 143
Interrupt Response Times ..................................................................................... 145
DTC and DMAC Activation by Interrupt ............................................................. 146
Conflict between Interrupt Generation and Disabling .......................................... 147
Instructions that Disable Interrupts....................................................................... 148
Times when Interrupts are Disabled ..................................................................... 148
Interrupts during Execution of EEPMOV Instruction .......................................... 148
Change of IRQ Pin Select Register (ITSR) Setting .............................................. 148
IRQ Status Register (ISR)..................................................................................... 149
Bus Width Control Register (ABWCR)................................................................ 158
Access State Control Register (ASTCR) .............................................................. 158
Wait Control Registers AH, AL, BH, and BL
(WTCRAH, WTCRAL, WTCRBH, and WTCRBL) ........................................... 159
Read Strobe Timing Control Register (RDNCR) ................................................. 165
CS Assertion Period Control Registers H, L (CSACRH, CSACRL).................... 167
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