R4F24569NVFQV Renesas Electronics America, R4F24569NVFQV Datasheet - Page 423

• Manufacturer Part Number: R4F24569NVFQV
• Description: MCU 256KB FLASH 64K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24569NVFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

H8S/2456, H8S/2456R, H8S/2454 Group
(4)
Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected.
Figure 7.31 shows an example of single address mode transfer activated by the DREQ pin low
level.
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
REJ09B0467-0350 Rev. 3.50
Jul 07, 2010
Figure 7.31 Example of DREQ Pin Low Level Activated Single Address Mode Transfer
Address bus
DMA control
[1]
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMAC cycle is started.
[4] [7] Acceptance is resumed after the single cycle is completed.
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
DREQ Pin Low Level Activation Timing
Channel
DREQ
DACK
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
φ
Idle
[1]
Request
Bus release
Minimum of
2 cycles
[2]
[3]
Single
Request clear
Transfer source/
DMA single
destination
period
Acceptance resumes
Idle
[4]
Request
Bus release
Minimum of
2 cycles
[5]
[6]
Single
Section 7 DMA Controller (DMAC)
Request clear
DMA single
Transfer source/
period
destination
Acceptance resumes
Idle
[7]
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release
Bus