D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 805

• Manufacturer Part Number: D12332VFC25
• Description: MCU 3V 0K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412332VFC25; HD6412332VFC25

19.10
All interrupts, including NMI input, are disabled when flash memory is being programmed or
erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot
mode *
1. Interrupt during programming or erasing might cause a violation of the programming or
2. In the interrupt exception handling sequence during programming or erasing, the vector would
3. If an interrupt occurred during boot program execution, it would not be possible to execute the
For these reasons, in on-board programming mode alone there are conditions for disabling
interrupts, as an exception to the general rule. However, this provision does not guarantee normal
erasing and programming or MCU operation. All interrupt requests, including NMI, must
therefore be restricted inside and outside the MCU when programming or erasing flash memory.
The NMI interrupt is also disabled in the error-protection state while the P or E bit remains set in
FLMCR1.
Notes: 1. Interrupt requests must be disabled inside and outside the MCU until the programming
erasing algorithm, with the result that normal operation could not be assured.
not be read correctly *
normal boot mode sequence.
1
, to give priority to the program or erase operation. There are three reasons for this:
2. A RAM area cannot be erased by execution of software in accordance with the erase
3. Block area EB0 includes the vector table. When performing RAM emulation, the
2. The vector may not be read correctly in this case for the following two reasons:
Interrupt Handling when Programming/Erasing Flash Memory
a transition to program mode or erase mode. When actually programming a flash
memory area, the RAMS bit should be cleared to 0.
algorithm while flash memory emulation in RAM is being used.
control program has completed programming.
• If flash memory is read while being programmed or erased (while the P or E bit is
• If the interrupt entry in the vector table has not been programmed yet, interrupt
vector table is needed by the overlap RAM.
set in FLMCR1), correct read data will not be obtained (undetermined values will
be returned).
exception handling will not be executed correctly.
2
, possibly resulting in MCU runaway.
Rev.4.00 Sep. 07, 2007 Page 773 of 1210
REJ09B0245-0400