D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 186

• Manufacturer Part Number: D12332VFC25
• Description: MCU 3V 0K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412332VFC25; HD6412332VFC25

6.4
6.4.1
The basic bus interface enables direct connection of ROM, SRAM, and so on.
The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL. (See table
6.3.)
6.4.2
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external space, controls whether the
upper data bus (D
for the area being accessed (8-bit access space or 16-bit access space) and the data size.
8-Bit Access Space: Figure 6.4 illustrates data alignment control for the 8-bit access space. With
the 8-bit access space, the upper data bus (D
data that can be accessed at one time is one byte: a word transfer instruction is performed as two
byte accesses, and a longword transfer instruction, as four byte accesses.
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Byte size
Word size
Longword size
Basic Bus Interface
Overview
Data Size and Data Alignment
Figure 6.4 Access Sizes and Data Alignment Control (8-Bit Access Space)
15
to D
8
) or lower data bus (D
1st bus cycle
2nd bus cycle
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
15
to D
7
D
to D
15
Upper data bus
8
) is always used for accesses. The amount of
0
) is used according to the bus specifications
D
8
D
7
Lower data bus
D
0