D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 717

• Manufacturer Part Number: D12332VFC25
• Description: MCU 3V 0K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412332VFC25; HD6412332VFC25

Section 15 Smart Card Interface
Serial Data Transmission (Except Block Transfer Mode): As data transmission in smart card
mode involves error signal sampling and retransmission processing, the processing procedure is
different from that for the normal SCI. Figure 15.4 shows a flowchart for transmitting, and figure
15.5 shows the relation between a transmit operation and the internal registers.
[1] Perform smart card interface mode initialization as described above in Initialization.
[2] Check that the ERS error flag in SSR is cleared to 0.
[3] Repeat steps [2] and [3] until it can be confirmed that the TEND flag in SSR is set to 1.
[4] Write the transmit data to TDR, clear the TDRE flag to 0, and perform the transmit operation.
The TEND flag is cleared to 0.
[5] When transmitting data continuously, go back to step [2].
[6] To end transmission, clear the TE bit to 0.
With the above processing, interrupt handling or data transfer by the DMAC or DTC is possible.
If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt
requests are enabled, a transmit-data-empty interrupt (TXI) request will be generated. If an error
occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt
requests are enabled, a transmit/receive-error interrupt (ERI) request will be generated.
The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag
setting timing is shown in figure 15.6.
If the DMAC or DTC is activated by a TXI request, the number of bytes set in the DMAC or DTC
can be transmitted automatically, including automatic retransmission.
For details, see Interrupt Operation (Except Block Transfer Mode) and Data Transfer Operation by
DMAC or DTC below.
Note: For details of operation in block transfer mode, see section 14.3.2, Operation in
Asynchronous Mode.
Rev.4.00 Sep. 07, 2007 Page 685 of 1210
REJ09B0245-0400