D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 23

• Manufacturer Part Number: D12332VFC25
• Description: MCU 3V 0K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412332VFC25; HD6412332VFC25

Section 12 8-Bit Timers
12.1 Overview........................................................................................................................... 555
12.2 Register Descriptions ........................................................................................................ 558
12.3 Operation........................................................................................................................... 565
12.4 Interrupts ........................................................................................................................... 570
12.5 Sample Application........................................................................................................... 571
12.6 Usage Notes ...................................................................................................................... 572
Section 13 Watchdog Timer
13.1 Overview........................................................................................................................... 579
13.2 Register Descriptions ........................................................................................................ 582
12.1.1 Features................................................................................................................ 555
12.1.2 Block Diagram..................................................................................................... 556
12.1.3 Pin Configuration................................................................................................. 557
12.1.4 Register Configuration......................................................................................... 557
12.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1) ......................................................... 558
12.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1) ............................... 558
12.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1) ................................ 559
12.2.4 Time Control Registers 0 and 1 (TCR0, TCR1) .................................................. 559
12.2.5 Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1).................................. 561
12.2.6 Module Stop Control Register (MSTPCR) .......................................................... 564
12.3.1 TCNT Incrementation Timing ............................................................................. 565
12.3.2 Compare Match Timing ....................................................................................... 566
12.3.3 Timing of TCNT External Reset.......................................................................... 568
12.3.4 Timing of Overflow Flag (OVF) Setting ............................................................. 568
12.3.5 Operation with Cascaded Connection.................................................................. 569
12.4.1 Interrupt Sources and DTC Activation ................................................................ 570
12.4.2 A/D Converter Activation.................................................................................... 570
12.6.1 Contention between TCNT Write and Clear........................................................ 572
12.6.2 Contention between TCNT Write and Increment ................................................ 573
12.6.3 Contention between TCOR Write and Compare Match ...................................... 574
12.6.4 Contention between Compare Matches A and B ................................................. 575
12.6.5 Switching of Internal Clocks and TCNT Operation............................................. 575
12.6.6 Interrupts and Module Stop Mode ....................................................................... 577
13.1.1 Features................................................................................................................ 579
13.1.2 Block Diagram..................................................................................................... 580
13.1.3 Pin Configuration................................................................................................. 581
13.1.4 Register Configuration......................................................................................... 581
13.2.1 Timer Counter (TCNT)........................................................................................ 582
13.2.2 Timer Control/Status Register (TCSR)................................................................ 583
..................................................................................................... 555
............................................................................................. 579
Rev.4.00 Sep. 07, 2007 Page xxi of xxx