DF36054GFPJV Renesas Electronics America, DF36054GFPJV Datasheet - Page 358

• Manufacturer Part Number: DF36054GFPJV
• Description: MCU 3/5V 32K J-TEMP PB-FREE 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36054GFPJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 Controller Area Network for Tiny (TinyCAN)
15.5
15.5.1
Figure 15.4 shows a flowchart for reset clearing of the TinyCAN. After a reset is cleared, all
registers are initialized.
Rev. 4.00 Mar. 15, 2006 Page 324 of 556
REJ09B0026-0400
Operation
TinyCAN Initial Settings
Notes: 1. The TinyCAN is reset at any time when the RSTRQ bit in MCR is set to 1.
2. The PMR97 and PMR96 bits in TCMR should be set after Mailboxes and LAFM have been
3. The RESET bit in GSR is a status flag that indicates CAN bus communication is possible
4. The TinyCAN receives messages when MBCR and TXPR are not set.
5. When MBCR and TXPR are set, the TinyCAN starts message transmission
Configuration mode
after reset procedure. This bit is cleared to 0 when 23 clock cycles are elapsed after BCR0 and
BCR1 have been set.
and carries out CAN bus arbitration. If an arbitration loss occurs, receive
operation starts.
Set PMR97 and PMR96 in
TCMR*
The TinyCAN starts communication with the CAN bus after BCR1 and BVR0 have been set.
initialized. Then BCR1 and BVR0 should be set.
Clear RSTRQ in MCR to 0
RTR, IDE, MBCR, DART,
Clear RHI in TCIRR0 to 0
Set BCR0 and BCR1*
Clear necessary bit in
TCIMR to 0
LAFM, MDn0 to MDn7
Set Mailboxes
2
[n = 0 to 3])
Figure 15.4 Reset Clearing Flowchart
(ID, DLC,
Reset *
1
2
Normal operation
Reception*
RESET in GSR*
11 recessive
bits received
continuously?
4
Yes
Yes
Transmission*
3
= 0?
No
No
5
23 clocks