DF36054GFPJV Renesas Electronics America, DF36054GFPJV Datasheet - Page 266

MCU 3/5V 32K J-TEMP PB-FREE 64-L

DF36054GFPJV

Manufacturer Part Number
DF36054GFPJV
Description
MCU 3/5V 32K J-TEMP PB-FREE 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of DF36054GFPJV

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 12 Timer Z
12.5
There are three kinds of timer Z interrupt sources; input capture/compare match, overflow, and
underflow. An interrupt is requested when the corresponding interrupt request flag is set to 1 while
the corresponding interrupt enable bit is set to 1.
12.5.1
IMF Flag Set Timing: The IMF flag is set to 1 by the compare match signal that is generated
when the GR matches with the TCNT. The compare match signal is generated at the last state of
matching (timing to update the counter value when the GR and TCNT match). Therefore, when
the TCNT and GR matches, the compare match signal will not be generated until the TCNT input
clock is generated. Figure 12.48 shows the timing to set the IMF flag.
Rev. 4.00 Mar. 15, 2006 Page 232 of 556
REJ09B0026-0400
TCNT input clock
Compare match
signal
TCNT
ITMZ
GR
IMF
Interrupts
Status Flag Set Timing
Figure 12.48 IMF Flag Set Timing when Compare Match Occurs
N
N
N+1

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