DF36054GFPJV Renesas Electronics America, DF36054GFPJV Datasheet - Page 315

• Manufacturer Part Number: DF36054GFPJV
• Description: MCU 3/5V 32K J-TEMP PB-FREE 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36054GFPJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.5.4
Figure 14.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In
serial reception, the SCI3 operates as described below.
1. The SCI3 performs internal initialization synchronous with a synchronization clock input or
2. The SCI3 stores the receive data in RSR.
3. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
4. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.13 shows a sample flow
chart for serial data reception.
RDRF
OER
LSI
operation
User
processing
Serial
clock
Serial
data
output, starts receiving data.
in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this
time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the
RDRF flag remains to be set to 1.
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated.
Serial Data Reception (Clocked Synchronous Mode)
Figure 14.12 Example of SCI3 Reception in Clocked Synchronous Mode
RXI interrupt
request
generated
Bit 7
Bit 0
RDRF flag
cleared
to 0
RDR data read
1 frame
Bit 7
RXI interrupt request generated
Bit 0
Section 14 Serial Communication Interface 3 (SCI3)
Bit 1
Rev. 4.00 Mar. 15, 2006 Page 281 of 556
1 frame
RDR data has
not been read
(RDRF = 1)
Bit 6
Bit 7
ERI interrupt request
generated by
overrun error
Overrun error
processing
REJ09B0026-0400