MC68HC16Z1MAG16 Freescale Semiconductor, MC68HC16Z1MAG16 Datasheet - Page 270
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MC68HC16Z1MAG16
Manufacturer Part Number
MC68HC16Z1MAG16
Description
IC MPU 16BIT 16MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HC16r
Datasheet
1.MC68HC16Z1VEH16.pdf
(500 pages)
Specifications of MC68HC16Z1MAG16
Core Processor
CPU16
Core Size
16-Bit
Speed
16MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-LQFP
Processor Series
HC16Z
Core
CPU16
Data Bus Width
16 bit
Data Ram Size
1 KB
Interface Type
SCI, QSPI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC16Z1MAG16
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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11-6
The CPU16 recognizes only interrupt request signals of a priority greater than the con-
dition code register interrupt priority (IP) mask value. When the CPU acknowledges an
interrupt request, the priority of the acknowledged request is written to the IP mask and
driven out on the IMB address lines.
When the IP mask value driven out on the address lines is the same as the IRL value,
the GPT contends for arbitration priority. GPT arbitration priority is determined by the
value of IARB[3:0] in GPTMCR. Each MCU module that can make interrupt requests
must be assigned a non-zero IARB value to implement an arbitration scheme. Arbitra-
tion is performed by serial assertion of IARB[3:0] bit values.
When the GPT wins interrupt arbitration, it responds to the CPU interrupt acknowledge
cycle by placing an interrupt vector number on the data bus. The vector number is
used to calculate displacement into the CPU16 exception vector table. Vector num-
bers are formed by concatenating the value in ICR IVBA[3:0] with a 4-bit value sup-
plied by the GPT when an interrupt request is made. Hardware prevents the vector
number from changing while it is being driven out on the IMB. Vector number assign-
ment is shown in
At reset, IVBA[3:0] is initialized to $0. To enable interrupt-driven timer operation, the
upper nibble of a user-defined vector number ($40 – $FF) must be written to IVBA, and
interrupt handler routines must be located at the addresses pointed to by the corre-
sponding vector.
The internal GPT interrupt priority hierarchy is shown in
terrupt source number, the higher the priority. A single GPT interrupt source can be
given priority over all other GPT interrupt sources by assigning the priority adjust field
(IPA[3:0]) in the ICR a value equal to its source number.
IC4/OC5
Name
PAOV
IVBA[3:0] must be written before GPT interrupts are enabled, or the
GPT could supply a vector number ($00 to $0F) that corresponds to
an assigned or reserved exception vector.
OC1
OC2
OC3
OC4
IC1
IC2
IC3
PAI
TO
—
Table
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 11-2 GPT Interrupt Sources
Number
11-2.
Source
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
GENERAL-PURPOSE TIMER
Go to: www.freescale.com
Input capture 4/output compare 5
Pulse accumulator overflow
Pulse accumulator input
NOTE
Output compare 1
Output compare 2
Output compare 3
Output compare 4
Adjusted channel
Input capture 1
Input capture 2
Input capture 3
Timer overflow
Source
Table
11-2. The lower the in-
IVBA : 0000
IVBA : 0010
IVBA : 0011
IVBA : 0100
IVBA : 0101
IVBA : 0110
IVBA : 0111
IVBA : 1000
IVBA : 1001
IVBA : 1010
IVBA : 1011
IVBA : 0001
Number
Vector
M68HC16 Z SERIES
USER’S MANUAL
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