MC68HC16Z1MAG16 Freescale Semiconductor, MC68HC16Z1MAG16 Datasheet - Page 269
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MC68HC16Z1MAG16
Manufacturer Part Number
MC68HC16Z1MAG16
Description
IC MPU 16BIT 16MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HC16r
Datasheet
1.MC68HC16Z1VEH16.pdf
(500 pages)
Specifications of MC68HC16Z1MAG16
Core Processor
CPU16
Core Size
16-Bit
Speed
16MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-LQFP
Processor Series
HC16Z
Core
CPU16
Data Bus Width
16 bit
Data Ram Size
1 KB
Interface Type
SCI, QSPI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC16Z1MAG16
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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11.4.2 GPT Interrupts
M68HC16 Z SERIES
USER’S MANUAL
For each bit in TFLG1 and TFLG2 there is a corresponding bit in TMSK1 and TMSK2
in the same bit position. If a mask bit is set and an associated event occurs, a hard-
ware interrupt request is generated.
In order to re-enable a status flag after an event occurs, the status flags must be
cleared. Status registers are cleared in a particular sequence. The register must first
be read for set flags, then zeros must be written to the flags that are to be cleared. If
a new event occurs between the time that the register is read and the time that it is
written, the associated flag is not cleared.
The GPT has 11 internal sources that can cause it to request interrupt service (refer
to
TMSK1 and TMSK2 are 8-bit registers that can be addressed individually or as one
16-bit register. The registers are initialized to zero at reset. For each bit in TMSK1 and
TMSK2 there is a corresponding bit in TFLG1 and TFLG2 in the same bit position.
TMSK2 also controls the operation of the timer prescaler. Refer to
more information.
The value of the interrupt priority level (IPL[2:0]) field in the interrupt control register
(ICR) determines the priority of GPT interrupt requests. IPL[2:0] values correspond to
MCU interrupt request signals IRQ[7:1]. IRQ7 is the highest priority interrupt request
signal; IRQ1 is the lowest-priority signal. A value of %111 causes IRQ7 to be asserted
when a GPT interrupt request is made; lower field values cause corresponding lower-
priority interrupt request signals to be asserted. Setting field value to %000 disables
interrupts.
Table
11-2). Setting bits in TMSK1 and TMSK2 enables specific interrupt sources.
Mnemonic
PAOVF
I4/O5F
OC1F
OC2F
OC3F
OC4F
IC1F
IC2F
IC3F
PAIF
Flag
TOF
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 11-1 GPT Status Flags
GENERAL-PURPOSE TIMER
Go to: www.freescale.com
Assignment
Register
TFLG1
TFLG1
TFLG1
TFLG1
TFLG1
TFLG1
TFLG1
TFLG1
TFLG2
TFLG2
TFLG2
Input capture 4/output compare 5
Pulse accumulator overflow
Pulse accumulator input
Output compare 1
Output compare 2
Output compare 3
Output compare 4
Input capture 1
Input capture 2
Input capture 3
Timer overflow
Source
11.7 Prescaler
11-5
for
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