MC68HC16Z1MAG16 Freescale Semiconductor, MC68HC16Z1MAG16 Datasheet - Page 236
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MC68HC16Z1MAG16
Manufacturer Part Number
MC68HC16Z1MAG16
Description
IC MPU 16BIT 16MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HC16r
Datasheet
1.MC68HC16Z1VEH16.pdf
(500 pages)
Specifications of MC68HC16Z1MAG16
Core Processor
CPU16
Core Size
16-Bit
Speed
16MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-LQFP
Processor Series
HC16Z
Core
CPU16
Data Bus Width
16 bit
Data Ram Size
1 KB
Interface Type
SCI, QSPI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC16Z1MAG16
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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9.4.3.3 Baud Clock
9.4.3.4 Parity Checking
9-26
The SCI baud rate is programmed by writing a 13-bit value to the SCBR field in SCI
control register 0 (SCCR0). The baud rate is derived from the MCU system clock by a
modulus counter. Writing a value of zero to SCBR[12:0] disables the baud rate gener-
ator. Baud rate is calculated as follows:
where SCBR[12:0] is in the range {1, 2, 3, ..., 8191}.
The SCI receiver operates asynchronously. An internal clock is necessary to synchro-
nize with an incoming data stream. The SCI baud rate generator produces a receive
time sampling clock with a frequency 16 times that of the SCI baud rate. The SCI de-
termines the position of bit boundaries from transitions within the received waveform,
and adjusts sampling points to the proper positions within the bit period.
The PT bit in SCCR1 selects either even (PT = 0) or odd (PT = 1) parity. PT affects
received and transmitted data. The PE bit in SCCR1 determines whether parity check-
ing is enabled (PE = 1) or disabled (PE = 0). When PE is set, the MSB of data in a
frame is used for the parity function. For transmitted data, a parity bit is generated; for
received data, the parity bit is checked. When parity checking is enabled, the PF bit in
the SCI status register (SCSR) is set if a parity error is detected.
Enabling parity affects the number of data bits in a frame, which can in turn affect
frame size.
Table 9-5
Start
Start
1
1
1
1
1
Freescale Semiconductor, Inc.
For More Information On This Product,
SCBR[12:0]
shows possible data and parity formats.
Table 9-4 Serial Frame Formats
SCI Baud Rate
QUEUED SERIAL MODULE
Go to: www.freescale.com
Data
Data
7
7
8
7
8
10-Bit Frames
11-Bit Frames
=
-------------------------------------------------------------------------- -
32 SCI Baud Rate Desired
Parity/Control
Parity/Control
=
or
------------------------------------------- -
32 SCBR[12:0]
—
—
1
1
1
f
sys
f
sys
Stop
Stop
2
1
1
2
1
M68HC16 Z SERIES
USER’S MANUAL
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