MC68HC16Z1MAG16 Freescale Semiconductor, MC68HC16Z1MAG16 Datasheet - Page 155
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MC68HC16Z1MAG16
Manufacturer Part Number
MC68HC16Z1MAG16
Description
IC MPU 16BIT 16MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HC16r
Datasheet
1.MC68HC16Z1VEH16.pdf
(500 pages)
Specifications of MC68HC16Z1MAG16
Core Processor
CPU16
Core Size
16-Bit
Speed
16MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-LQFP
Processor Series
HC16Z
Core
CPU16
Data Bus Width
16 bit
Data Ram Size
1 KB
Interface Type
SCI, QSPI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC16Z1MAG16
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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5.7.3 Reset Mode Selection
M68HC16 Z SERIES
USER’S MANUAL
Internal single byte or aligned word writes are guaranteed valid for synchronous re-
sets. External writes are also guaranteed to complete, provided the external configu-
ration logic on the data bus is conditioned as shown in
The logic states of certain data bus pins during reset determine SIM operating config-
uration. In addition, the state of the MODCLK pin determines system clock source and
the state of the BKPT pin determines what happens during subsequent breakpoint as-
sertions.
Software watchdog
Loss of clock
Power up
External
HALT
Type
Test
Mode Select Pin
NOTES:
Table 5-19
1. DATA11 must remain high during reset to ensure normal operation.
MODCLK
DATA11
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
BKPT
External
Source
Monitor
Monitor
Clock
Test
EBI
Freescale Semiconductor, Inc.
is a summary of reset mode selection options.
Table 5-18 Reset Source Summary
For More Information On This Product,
Table 5-19 Reset Mode Selection
Background Mode Disabled
VCO = System Clock
SYSTEM INTEGRATION MODULE
Timing
Asynch
Asynch
Asynch
Synch
Synch
Synch
Normal Operation
Default Function
CSBOOT 16-Bit
(Pin Left High)
AVEC, DS, AS,
DSACK[1:0],
Go to: www.freescale.com
MODCLK
CS[10:6]
IRQ[7:1]
SIZ[1:0]
CS[7:6]
CS[8:6]
CS[9:6]
CS0
CS1
CS2
CS3
CS4
CS5
CS6
Internal HALT assertion
(e.g. double bus fault)
Loss of reference
RESET pin
Test mode
Time out
1
Cause
V
DD
Background Mode Enabled
EXTAL = System Clock
Alternate Function
MSTRST
MSTRST
MSTRST
MSTRST
MSTRST
MSTRST
Figure
(Pin Pulled Low)
CSBOOT 8-Bit
ADDR[20:19]
ADDR[21:19]
ADDR[22:19]
ADDR[23:19]
Reset Lines Asserted by
Reserved
ADDR19
BGACK
PORTE
PORTF
FC0
FC1
FC2
BG
BR
5-18.
Controller
CLKRST
CLKRST
CLKRST
CLKRST
CLKRST
—
EXTRST
EXTRST
EXTRST
EXTRST
EXTRST
EXTRST
5-49
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