MC68HC16Z1MAG16 Freescale Semiconductor, MC68HC16Z1MAG16 Datasheet - Page 150
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MC68HC16Z1MAG16
Manufacturer Part Number
MC68HC16Z1MAG16
Description
IC MPU 16BIT 16MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HC16r
Datasheet
1.MC68HC16Z1VEH16.pdf
(500 pages)
Specifications of MC68HC16Z1MAG16
Core Processor
CPU16
Core Size
16-Bit
Speed
16MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-LQFP
Processor Series
HC16Z
Core
CPU16
Data Bus Width
16 bit
Data Ram Size
1 KB
Interface Type
SCI, QSPI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC16Z1MAG16
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 150 of 500
- Download datasheet (6Mb)
5.6.5.1 Bus Errors
5-44
1. S = The number of current even bus state (for example, S2, S4, etc.)
2. A = Signal is asserted in this bus state.
3. NA = Signal is not asserted in this state.
4. RA = Signal was asserted in previous state and remains asserted in this state.
5. X = Don’t care
The CPU16 treats bus errors as a type of exception. Bus error exception processing
begins when the CPU16 detects assertion of the IMB BERR signal.
BERR assertions do not force immediate exception processing. The signal is synchro-
nized with normal bus cycles and is latched into the CPU16 at the end of the bus cycle
in which it was asserted. Because bus cycles can overlap instruction boundaries, bus
error exception processing may not occur at the end of the instruction in which the bus
cycle begins. Timing of BERR detection/acknowledge is dependent upon several
factors:
Because of these factors, it is impossible to predict precisely how long after occur-
rence of a bus error the bus error exception is processed.
BUS ERROR
BUS ERROR
BUS ERROR
BUS ERROR
Termination
NOTES:
NORMAL
Type of
HALT
• Which bus cycle of an instruction is terminated by assertion of BERR.
• The number of bus cycles in the instruction during which BERR is asserted.
• The number of bus cycles in the instruction following the instruction in which
• Whether BERR is asserted during a program space access or a data space
BERR is asserted.
access.
1
2
3
4
Table 5-17 DSACK, BERR, and HALT Assertion Results
Control
DSACK
DSACK
DSACK
DSACK
DSACK
DSACK
Signal
BERR
BERR
BERR
BERR
BERR
BERR
HALT
HALT
HALT
HALT
HALT
HALT
Freescale Semiconductor, Inc.
For More Information On This Product,
SYSTEM INTEGRATION MODULE
A/RA
NA/A
NA/A
Asserted on Rising
NA
A/S
NA
NA
NA
NA
NA
NA
S
A
A
A
A
A
A
A
Go to: www.freescale.com
1
2
Edge of State
3
S + 2
RA
NA
RA
NA
RA
RA
RA
NA
RA
RA
X
X
X
X
X
X
A
A
5
4
Normal cycle terminate and continue.
Normal cycle terminate and halt.
Continue when HALT is negated.
Terminate and take bus error exception.
Terminate and take bus error exception.
Terminate and take bus error exception.
Terminate and take bus error exception.
Description
of Result
M68HC16 Z SERIES
USER’S MANUAL
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