M30263F6AFP#U5A Renesas Electronics America, M30263F6AFP#U5A Datasheet - Page 83
![IC M16C/26A MCU FLASH 42-SSOP](/photos/12/39/123973/m30263f6afp_u5a_sml.jpg)
M30263F6AFP#U5A
Manufacturer Part Number
M30263F6AFP#U5A
Description
IC M16C/26A MCU FLASH 42-SSOP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheet
1.M30260F3AGPU5A.pdf
(354 pages)
Specifications of M30263F6AFP#U5A
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
33
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
42-SSOP
For Use With
R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R
R
M
9.2 Interrupts and Interrupt Vector
e
E
1
. v
J
Figure 9.2.1. Interrupt Vector
Table 9.2.1.1. Fixed Vector Tables
NOTES:
6
0
________
_______
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective
interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the
corresponding interrupt vector. Figure 9.2.1 shows the interrupt vector.
9.2.1 Fixed Vector Tables
Interrupt source
Undefined instruction FFFDC
Overflow
BRK instruction
Address match
Single step (1)
Watchdog timer
Oscillation stop and
Voltage down
detection
DBC (1)
NMI
Reset (2)
2
C
re-oscillation detection
9
1. Do not normally use this interrupt because it is provided exclusively for use by development tools.
2. The b3 to b0 in address 0FFFFF
0 .
B
2 /
The fixed vector tables are allocated to the addresses from FFFDC
fixed vector tables. In the flash memory version of microcomputer, the vector addresses (H) of fixed
vectors are used by the ID code check function. For details, refer to the section 17.3 Flash Memory
Rewrite Disabling Function.
0
0
6
2
A
0
F
2
e
G
0 -
b
o r
1 .
2
0
, 5
u
0
p
2
0
(
M
0
7
1
6
C
Vector address (H)
page 64
Vector address (L)
2 /
Address (L) to address (H)
Vector table addresses
6
FFFEC
FFFE8
FFFFC
FFFE0
FFFE4
FFFF8
FFFF0
FFFF4
, A
M
1
f o
6
16
16
16
16
16
16
16
16
16
C
3
2
to FFFEB
to FFFFB
2 /
to FFFE3
to FFFE7
to FFFF3
to FFFF7
to FFFDF
to FFFEF
to FFFFF
16
9
6
are reserve bits. Set these bits to “1111
, B
M
1
6
16
16
16
16
16
16
16
16
16
C
MSB
2 /
6
) T
If the contents of address
FFFE7
ecution starts from the address
shown by the vector in the
relocatable vector table.
Interrupt on UND instruction
Interrupt on INTO instruction
0 0 0 0
0 0 0 0
16
Low address
Mid address
is FF
Remarks
16
High address
, program ex-
0 0 0 0
16
to FFFFF
2
”.
LSB
16
_______
. Table 9.2.1.1 lists the
M16C/60, M16C/20
serise software
maual
Address match interrupt
Watchdog timer
Clock generating circuit
Voltage detection circuit
NMI interrupt
Reset
Reference
9. Interrupt
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