M30263F6AFP#U5A Renesas Electronics America, M30263F6AFP#U5A Datasheet - Page 162
![IC M16C/26A MCU FLASH 42-SSOP](/photos/12/39/123973/m30263f6afp_u5a_sml.jpg)
M30263F6AFP#U5A
Manufacturer Part Number
M30263F6AFP#U5A
Description
IC M16C/26A MCU FLASH 42-SSOP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheet
1.M30260F3AGPU5A.pdf
(354 pages)
Specifications of M30263F6AFP#U5A
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
33
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
42-SSOP
For Use With
R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R
R
M
e
E
. v
1
J
Table 13.1.1. 2. Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode
NOTES:
i=0 to 2
0
6
Register
UiTB
UiRB
UiBRG
UiMR
UiC0
UiC1
U2SMR
U2SMR2
U2SMR3
U2SMR4
UCON
2
9
C
0 .
B
1. Set bit 4 and bit 5 in the U0C1 and U1C1 register are set to “0”. The U0IRS, U1IRS, U0RRM and U1RRM
2. Not all register bits are described above. Set those bits to “0” when writing to the registers in clock synchro-
3. Set the bit 6 and bit 7 in the U0C1 and U1C1 register to "0".
4. Set the bit 7 in the U0MR and U1MR register to "0".
2 /
0
0
2
6
bits are in the UCON register.
nous serial I/O mode.
(3)
(3)
0
A
(3)
F
2
e
0 -
G
b
1 .
2
o r
0
, 5
u
0
0 to 7
0 to 7
OER
0 to 7
SMD2 to SMD0
CKDIR
IOPOL(i=2)
CLK1 to CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS
U2RRM
U2LCH
U2ERE
0 to 7
0 to 7
0 to 2
NODC
4 to 7
0 to 7
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1
RCSP
7
p
2
0
(
0
M
Bit
7
1
6
(1)
(3)
(3)
C
(1)
page 143
2 /
(4)
6
, A
M
1
f o
6
Set transmission data
Reception data can be read
Overrun error flag
Set a transfer rate
Set to “001
Select the internal clock or external clock
Set to “0”
Select the count source for the UiBRG register
Select CTS or RTS to use
Transmit register empty flag
Enable or disable the CTS or RTS function
Select TxDi pin output mode
Select the transfer clock polarity
Select the LSB first or MSB first
Set this bit to “1” to enable transmission/reception
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select the source of UART2 transmit interrupt
Set this bit to “1” to use UART2 continuous receive mode
Set this bit to “1” to use UART2 inverted data logic
Set to “0”
Set to “0”
Set to “0”
Set to “0”
Select clock output mode
Set to “0”
Set to “0”
Select the source of UART0/UART1 transmit interrupt
Set this bit to “1” to use continuous receive mode
Select the transfer clock output pin when CLKMD1 = 1
Set this bit to “1” to output UART1 transfer clock from two pins
Set this bit to “1” to accept as input the UART0 CTS
Set to “0”
3
C
2
2 /
9
6
, B
_______
M
1
2
”
6
C
_______
2 /
6
) T
Function
_______
_______
_________
0
signal from the P6
4
pin or P7
13. Serial I/O
0
pin
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