MC908MR32CFUE Freescale Semiconductor, MC908MR32CFUE Datasheet - Page 98

• Manufacturer Part Number: MC908MR32CFUE
• Description: IC MCU 8MHZ 32K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908MR32CFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 44
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: HC08MR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 6
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Low-Voltage Inhibit (LVI)
Once an LVI reset occurs, the MCU remains in reset until V
V
14.3.2.6 Low-Voltage Inhibit (LVI)
flag in the LVI status register (LVISCR).
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
See
9.3.1 Polled LVI Operation
In applications that can operate at V
LVIOUT bit. In the configuration register, the LVIPWR bit must be 1 to enable the LVI module, and the
LVIRST bit must be 0 to disable LVI resets. See
in the LVISCR selects V
9.3.2 Forced Reset Operation
In applications that require V
reset the MCU when V
consecutive CPU cycles. In the CONFIG register, the LVIPWR and LVIRST bits must be 1s to enable the
LVI module and to enable LVI resets. TRPSEL in the LVISCR selects V
9.3.3 False Reset Protection
The V
module to reset the MCU, V
V
LVISCR selects V
9.3.4 LVI Trip Selection
The TRPSEL bit allows the user to chose between 5 percent and 10 percent tolerance when monitoring
the supply voltage. The 10 percent option is enabled out of reset. Writing a 1 to TRPSEL will enable 5
percent option.
98
DD
DD
$FE0F
Addr.
must be above V
19.5 DC Electrical
must be above V
DD
pin level is digitally filtered to reduce false resets due to power supply noise. In order for the LVI
LVI Status and Control Register
The microcontroller is guaranteed to operate at a minimum supply voltage.
The trip point (VLVR1 or VLVR2) may be lower than this. See
Electrical
Register Name
LVRX
LVRX
LVRX
DD
+ V
Characteristics.
LVRX
Characteristics.
falls to the V
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
See page 99.
+ V
LVHX
+ V
DD
DD
.
(LVISCR)
LVHX
LVHX
must remain at or below V
.
to remain above V
Figure 9-2. LVI I/O Register Summary
Reset. The output of the comparator controls the state of the LVIOUT
for only one CPU cycle to bring the MCU out of reset. TRPSEL in the
for only one CPU cycle to bring the MCU out of reset. See
DD
Reset:
Read: LVIOUT
Write:
LVRX
levels below V
level and remains at or below that level for nine or more
Bit 7
R
R
0
Chapter 5 Configuration Register
NOTE
= Reserved
LVRX
R
6
0
0
LVRX
, enabling LVI resets allows the LVI module to
LVRX
TRPSEL
, software can monitor V
DD
5
0
for nine or more consecutive CPU cycles.
rises above a voltage, V
R
4
0
0
LVRX
R
3
0
0
.
19.5 DC
(CONFIG). TRPSEL
Freescale Semiconductor
DD
R
2
0
0
by polling the
LVRX
R
1
0
0
+ V
LVHX
Bit 0
R
0
0
.