MC9S12XDT256MAG Freescale Semiconductor, MC9S12XDT256MAG Datasheet - Page 884

• Manufacturer Part Number: MC9S12XDT256MAG
• Description: IC MCU 256K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (24-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.4.2.10 Port H
This port is associated with the SPI1, SPI2, SCI4, and SCI5. Port H pins PH[7:0] can be used for either
general purpose I/O, or with the SPI and SCI subsystems. Port H pins can be used with the routed SPI1
and SPI2 modules. Refer to
Port H offers 8 I/O pins with edge triggered interrupt capability
22.4.2.11 Port J
This port is associated with the chip selects CS0, CS1, CS2 and CS3 as well as with CAN4, CAN0, IIC1,
IIC0, and SCI2. Port J pins PJ[7:4] and PJ[2:0] can be used for either general purpose I/O, or with the
CAN, IIC, or SCI subsystems. If IIC takes precedence the associated pins become IIC open-drain output
pins. The CAN4 pins can be re-routed. Refer to
Port J pins can be used with the routed CAN0 modules. Refer to
Register
Port J offers 7 I/O pins with edge triggered interrupt capability
22.4.2.12 Port AD0
This port is associated with the ATD0. Port AD0 pins PAD07–PAD00 can be used for either general
purpose I/O, or with the ATD0 subsystem.
22.4.2.13 Port AD1
This port is associated with the ATD1. Port AD1 pins PAD23–PAD08 can be used for either general
purpose I/O, or with the ATD1 subsystem.
886
(MODRR)”.
Port H is not available in 80-pin packages.
PJ[5,4,2] are not available in 112-pin packages. PJ[5,4,2,1,0] are not
available in 80-pin packages.
PAD[23:16] are not available in 112-pin packages. PAD[23:08] are not
available in 80-pin packages.
Section 22.3.2.37, “Module Routing Register
MC9S12XDP512 Data Sheet, Rev. 2.21
Section 22.3.2.37, “Module Routing Register
NOTE
NOTE
NOTE
(Section 22.4.3, “Pin
(Section 22.4.3, “Pin
Section 22.3.2.37, “Module Routing
(MODRR)”.
Freescale Semiconductor
Interrupts”).
Interrupts”).
(MODRR)”.