MC9S12XDT256MAG Freescale Semiconductor, MC9S12XDT256MAG Datasheet - Page 843

• Manufacturer Part Number: MC9S12XDT256MAG
• Description: IC MCU 256K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (24-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.3.2.25 Port S Data Direction Register (DDRS)
Read: Anytime.
Write: Anytime.
This register configures each port S pin as either input or output.
If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin
is forced to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive
channel is enabled.
The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
Freescale Semiconductor
DDRS[7:0]
Reset
Field
7–0
W
R
DDRS7
Data Direction Port S
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
0
7
on PTS or PTIS registers, when changing the DDRS register.
DDRS6
0
6
Figure 22-27. Port S Data Direction Register (DDRS)
Table 22-27. DDRS Field Descriptions
DDRS5
MC9S12XDP512 Data Sheet, Rev. 2.21
0
5
DDRS4
0
4
Description
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
DDRS3
0
3
DDRS2
0
2
DDRS1
0
1
DDRS0
0
0
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