MC9S12XDT256MAG Freescale Semiconductor, MC9S12XDT256MAG Datasheet - Page 179

• Manufacturer Part Number: MC9S12XDT256MAG
• Description: IC MCU 256K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (24-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.3.2.13
The A/D conversion results are stored in 8 read-only result registers. The result data is formatted in the
result registers based on two criteria. First there is left and right justification; this selection is made using
the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using
the DSGN control bit in ATDCTL5. Signed data is stored in 2’s complement format and only exists in left
justified format. Signed data selected for right justified format is ignored.
Read: Anytime
Write: Anytime in special mode, unimplemented in normal modes
5.3.2.13.1
5.3.2.13.2
Freescale Semiconductor
Reset
Reset
Reset
Reset
W
W
W
W
R
R
R
R
R
R
R
R
BIT 9 MSB
BIT 7 MSB
BIT 7 MSB
BIT 1
BIT 7
U
0
0
0
0
0
0
7
7
7
7
Figure 5-17. Right Justified, ATD Conversion Result Register, High Byte (ATDDRxH)
Figure 5-18. Right Justified, ATD Conversion Result Register, Low Byte (ATDDRxL)
Figure 5-15. Left Justified, ATD Conversion Result Register, High Byte (ATDDRxH)
Figure 5-16. Left Justified, ATD Conversion Result Register, Low Byte (ATDDRxL)
ATD Conversion Result Registers (ATDDRx)
Left Justified Result Data
Right Justified Result Data
= Unimplemented or Reserved
= Unimplemented or Reserved
= Unimplemented or Reserved
= Unimplemented or Reserved
BIT 8
BIT 6
BIT 0
BIT 6
BIT 6
U
6
0
6
0
6
0
0
0
6
0
BIT 7
BIT 5
BIT 5
BIT 5
0
0
0
0
0
0
0
0
5
5
5
5
MC9S12XDP512 Data Sheet, Rev. 2.21
BIT 6
BIT 4
BIT 4
BIT 4
0
0
0
0
0
0
0
0
4
4
4
4
BIT 5
BIT 3
BIT 3
BIT 3
0
0
0
0
0
0
0
0
3
3
3
3
Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
BIT 4
BIT 2
BIT 2
BIT 2
0
0
0
0
0
0
0
0
2
2
2
2
BIT 9 MSB
BIT 3
BIT 1
BIT 1
BIT 1
0
0
0
0
0
0
0
1
1
1
1
BIT 2
BIT 0
BIT 8
BIT 0
BIT 0
0
0
0
0
0
0
0
0
0
0
0
10-bit data
10-bit data
10-bit data
8-bit data
8-bit data
8-bit data
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